Samsung S3C84E5 user manual Tacon Timer a Control Register E1H Set 1, Bank

S3C84E5/C84E9/P84E9CONTROL REGISTER

TACON — Timer A Control Register E1H Set 1, Bank 1

Bit Identifier

Reset Value

Read/Write Addressing Mode

.7–.6

.7		.6	.5	.4	.3	.2	.1	.0
0		0	0	0	0	0	0	0
R/W		R/W	R/W	R/W	R/W	R/W	R/W	R/W
Register addressing mode only
Timer A Input Clock Selection Bits
0	0	fxx/1024
0	1	fxx/256
1	0	fxx/64
1	1	External clock (TACK)

.5–.4	Timer A Operating Mode Selection Bits
	0	0	Interval mode (TAOUT mode)
	0	1	Capture mode (capture on rising edge, counter running, OVF can occur)
	1	0	Capture mode (capture on falling edge, counter running, OVF can occur)
	1	1	PWM mode (OVF interrupt can occur)

.3	Timer A Counter Clear Bit
	0	No effect
	1	Clear the timer A counter (Auto-clear bit)
.2	Timer A Overflow Interrupt Enable Bit
	0	Disable overflow interrupt
	1	Enable overflow interrupt
.1	Timer A Match/Capture Interrupt Enable Bit
	0	Disable interrupt
	1	Enable interrupt

.0	Timer A Start/Stop Bit
	0	Stop timer A
	1	Start timer A

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