S3C84E5/C84E9/P84E9 RESET and POWER-DOWN
8-1
8 RESET and POWER-DOWN
SYSTEM RESET
OVERVIEW
During a power-on Reset, the voltage at VDD goes to High level and the nRESET pin is forced to Low level. The
nRESET signal is input through a Schmitt trigger circuit where it is then synchronized with the CPU clock. This
procedure brings S3C84E5/C84E9/P84E9 into a known operating status.
To allow time for internal CPU clock oscillation to stabilize, the nRESET pin must be held to Low level for a minimum
time interval after the power supply comes within tolerance. The minimum required oscillation stabilization time for a
reset operation is 1 millisecond.
Whenever a reset occurs during normal operation (that is, when both VDD and nRESET are High level), the nRESET
pin is forced Low and the Reset operation starts. All system and peripheral control registers are then Reset to their
default hardware values
In summary, the following sequence of events occurs during a Reset operation:
— Interrupt is disabled.
— The watchdog function (basic timer) is enabled.
— Ports 0-4 are set to input mode with pull-up resistor, P0.0 and P0.1 are set to XTin and XTout respectively.
— Peripheral control and data registers are disabled and reset to their default hardware values.
— The program counter (PC) is loaded with the program reset address in the ROM, 0100H.
— When the programmed oscillation stabilization time interval has elapsed, the instruction stored in ROM location
0100H (and 0101H) is fetched and executed.
NORMAL MODE RESET OPERATION
In normal (masked ROM) mode, the TEST pin is tied to VSS. A reset enables access to the 32-Kbyte on-chip ROM.
NOTE
To program the duration of the oscillation stabilization interval, you make the appropriate settings to the
basic timer control register, BTCON, before entering Stop mode. Also, if you do not want to use the basic
timer watchdog function (which causes a system reset if a basic timer counter overflow occurs), you can
disable it by writing '1010B' to the upper nibble of BTCON.