S3C84E5/C84E9/P84E9 CONTROL REGISTER
4-1
4 CONTROL REGISTERS
OVERVIEW
Control register descriptions are arranged in alphabetical order according to register mnemonic. More detailed
information about control registers is presented in the context of the specific peripheral hardware descriptions in Part
II of this manual.
The locations and read/write characteristics of all mapped registers in the S3C84E5/C84E9/P84E9 register file are
listed in Table 4-1. The hardware Reset value for each mapped register is described in Chapter 8, RESET and
Power-Down."
Table 4-1. Set 1 Registers
Register Name Mnemonic Decimal Hex R/W
Timer B control register TBCON 208 D0H R/W
Timer B data register (High Byte) TBDATAH 209 D1H R/W
Timer B data register (Low Byte) TBDATAL 210 D2H R/W
Basic timer control register BTCON 211 D3H R/W
Clock control register CLKCON 212 D4H R/W
System flags register FLAGS 213 D5H R/W
Register pointer 0 RP0 214 D6H R/W
Register pointer 1 RP1 215 D7H R/W
Stack pointer (High Byte) SPH 216 D8H R/W
Stack pointer (Low Byte) SPL 217 D9H R/W
Instruction pointer (High Byte) IPH 218 DAH R/W
Instruction pointer (Low Byte) IPL 219 DBH R/W
Interrupt request register IRQ 220 DCH R
Interrupt mask register IMR 221 DDH R/W
System mode register SYM 222 DEH R/W
Register page pointer PP 223 DFH R/W