Mechanical Data, Max, Min, 18-1 | Samsung S3C84E5 specification

S3C84E5/C84E9/P84E9					MECHANICAL DATA
18 MECHANICAL DATA
OVERVIEW
The S3C84E5/C84E9/P84E9 microcontrollers are available in a 42-SDIP-600, 44-QFP-1010 package.
#42				#22				0-15
								0-15
14.00 ?0.20		42-SDIP-600			15.24			. 10			. 05
						+	0	. 10		0
							0		-

							25

					0	.
					0
#1				#21
		39.50 MAX		?0.20	MAX
		39.10 ?0.20		?0.20	MAX
		39.10 ?0.20		3.50	5.08
				3.50	5.08
		0.50 ?0.10		MIN	?0.30
(1.77)		1.00 ?0.10	1.78	MIN	?0.30
(1.77)		1.00 ?0.10	1.78	0.51	3.30
				0.51	3.30
NOTE:	Dimensions are in millimeters.
		Figure 18-1. 42-SDIP-600 Package Dimensions

18-1

Page 302

Image 302

Samsung S3C84E5 user manual Mechanical Data, Max, Min, 18-1

Contents

Page Built-in Reset circuit LVR FeaturesLow Voltage Reset Errata VER BGR ResetVDD D.C. Electrical Characteristics Parameter Symbol Conditions Min Typ Max Unit VDD = 4.5V to RUN mode MHz CPU clock VDD = Vlvr to 5.5 Pull-up resistor Main Oscillator Clock Stabilization TimePAGE A.C. Electrical CharacteristicsMain Oscillator Frequency Sub Oscillator Frequency Parameter Symbol Min Typ Max Unit Data Retention Supply Voltage in Stop Mode10. Uart Timing Characteristics in Mode 0 Oscillator Test Condition Min Typ Max Unit Comparison of S3P84E9 and S3C84E5/C84E9 Features 11. A/D Converter Electrical Characteristics12. LVR Low Voltage Reset Circuit Characteristics Operating Voltage RangePAGE S3C84E5/C84E9/P84E9 Important Notice Iii Part Programming ModelUart Table of Contents Chapter Interrupt Structure Overview Part II Hardware Descriptions Vii Chapter Viii HEX2ROM List of Figures Title Number 11-8 10-210-4 Xii 13-3 12-412-5 13-7 17-2 17-11 Xvi Chapter Watch Timer Chapter Bit Timer A/BChapter Bit Timer 10,1 Chapter Converter Configuring A/D Converter 15-6 Register Full Register Name Identifier Number Instruction Full Register Name Mnemonic Number LDCI/LDEI LDC/LDELDCD/LDED LDCPD/LDEPD S3C84E5/C84E9/P84E9 Microcontroller Product OverviewS3C8-SERIES Microcontrollers Features CPU Block Diagram S3C84E5/C84E9/P84E9 Block Diagram Top View NRESETPIN Assignment 44-QFP S3P84E9 S3C84E5S3C84E9 Sdip S3C84E5/C84E9/P84E9 Pin Descriptions Circuit Share Type Description Number PinsPIN Descriptions BUZ INT0-INT10AVREF, Avss Test Pin Circuit Type B nRESET PIN Circuits Pin Circuit Type D P0.2-P0.7, P1, P4.3-P4.5 Pin Circuit Type E P3 Address Spaces Overview 0FFH Program Memory ROMHEX Total Addressable Bytes Register ArchitectureS3C84E5/C84E9/P84E9 Register Type Summary Number of Bytes 590 Set1 Bank Page01 PagePage00 Set Register page Pointer PP MSB LSB Djnz R0,RAMCL0 CLR SRPRAMCL0 CLR RAMCL1 CLR Register SET Set Bank Prime Register SpaceFFH F0H E0H D0H C0H C0H BFH F7H Working RegistersF8H SRP1 Using the Register PointersProgramming TIP Setting the Register Pointers SRP0 R0,R2 #80H RP0 ← 80HR0,R1 ← R0 + R1 + R2 + C Register Addressing Bit Register Pair Register Pointers FFH E0H D0H C0H BFHControl Registers System Prime Registers FFH F0H Common Working Register Area C0H-CFHRP1 → C8H-CFH E0H D0H C0H BFH Example Programming TIP Addressing the Common Working Register AreaExamples BIT Working Register Addressing RP0 RP1 R6 Opcode 13 -Bit Working Register Addressing 14 -Bit Working Register Addressing Example Stack Pointers SPL, SPH System and User StackStack Operations High Address Push RP1 SPL,#0FFH SPL ← FFHPush RP0 POP RP1 Addressing Modes DEC Cntr Register Addressing Mode ROpcode Operand @SHIFT Indirect Register Addressing Mode IRAddress Call @RR2 JP @RR2 Indirect Register Addressing ModeRegister Pair Indirect Working Register Addressing to Register File LCD LDE Indexed Addressing Mode Index LDC Indexed Addressing ModeOffset Indexed Addressing to Program or Data Memory Direct Address Mode DA 10. Direct Addressing for Load Instructions Call Display Direct Address ModeJOB1 Indirect Address Mode IA Call #40H Relative Address Mode RA ULT,$+OFFSET LD R0,#0AAH Immediate Mode IMOperand Opcode Control Registers Set 1 Registers Register Name Mnemonic Decimal Hex Set 1, Bank 0 Registers Register Name Mnemonic Decimal Hex Set 1, Bank 1 Registers Register Name Mnemonic Decimal Hex Zero Flag Z Bit Identifier Reset Value Read/Write Bit AddressingMode Carry Flag C Sign Flag S Adcon A/D Converter Control Register F7H Set 1, Bank Btcon Basic Timer Control Register D3H CPU Clock System Clock Selection Bits note Clkcon System Clock Control RegisterD4H Fxx/2 Flags System Flags Register D5H IMR Interrupt Mask Register DDH IPL Instruction Pointer Low Byte IPH Instruction Pointer High ByteDAH DBH IPR Interrupt Priority Register FFH IRQ Interrupt Request Register DCH Main System Oscillator Control Bit Osccon Oscillator Control Register FBH Set 1, BankSub-system Oscillator Driving Ability Control Bit Sub System Oscillator Control Bit P0.5/T1CAP0 Configuration Bits P0.7/TACAP Configuration BitsP0.6/TACK Configuration Bits P0.4/T1OUT1 Configuration Bits P0.1/XTout Configuration Bits P0.3/T1CK1 Configuration BitsP0.2/T1CAP1 Configuration Bits P0.0/XTin Configuration Bits P1CONH Port 1 Control Register High Byte E8H Set 1, Bank P1.5/TXD Configuration BitsP1.4/RXD Configuration Bits P1.1/T1CK0 Configuration Bits P1.3/BZOUT Configuration BitsP1.2/T1OUT0 Configuration Bits P1.0/TAOUT Configuration Bits P2.6/ INT6 P2CONH Port 2 Control Register High Byte EAH Set 1, BankP2.7/INT7 P2.5/ INT5 P2.2/INT2 P2CONL Port 2 Control Register Low Byte EBH Set 1, BankP2.3/INT3 P2.1/INT1 P2INT Port 2 Interrupt Control Register ECH P2INTPND Port 2 Interrupt Pending Register EDH 4P3.6/ADC6 P3CONH Port 3 Control Register High Byte EEH Set 1, BankP3.7/ADC7 2P3.5/ADC5 4P3.2/ADC2 P3CONL Port 3 Control Register Low Byte EFH Set 1, BankP3.3/ADC3 3P3.1/ADC1 P4.5 Input mode Push-pull output modeP4CONH Port 4 Control Register High Byte F0H Set 1, Bank P4.4 P4.2/INT10 P4CONL Port 4 Control Register Low Byte F1H Set 1, BankP4.3/TBPWM P4.1/INT9 P4.0 External Interrupt INT8 Enable Bit P4.2 External Interrupt INT10 Enable BitP4.1 External Interrupt INT9 Enable Bit P4INT Port 4 Interrupt Control Register P4.2/PND10 Interrupt Pending Bit P4INTPND Port 4 Interrupt Pending RegisterF3H P4.1/PND9 Interrupt Pending Bit Destination Register Page Selection Bits PP Register Page PointerDFH Source Register Page Selection Bits RP1 Register Pointer RP0 Register PointerD6H D7H Set SPH Stack Pointer High ByteD8H SPL Stack Pointer Low Byte Stpcon Stop Control Register E5H Set 1, Bank Stop Control Bits Global Interrupt Enable Bit note SYM System Mode RegisterFast Interrupt Enable Bit DEH T1CON0 Timer 10 Control Register E8H Set 1, Bank T1CON1 Timer 11 Control Register E9H Set 1, Bank Tacon Timer a Control Register E1H Set 1, Bank Tbcon Timer B Control Register D0H Tintpnd Timer A, Timer 1 Interrupt Pending Register E0H Receive Interrupt Enable Bit Multiprocessor Communication 1 Enable Bit for mode 2 onlySerial Data Receive Enable Bit Transmit Interrupt Enable Bit Control Register Uartpnd Uart Pending and parity control F4H Set 1, Bank Wtcon Watch Timer Control Register FAH Set 1, Bank Vectors Interrupt StructureLevels Sources Interrupt Types Levels Type 1 IRQn Type 2 IRQn Type 3 IRQn Vectors Sources S3C84E5/C84E9/P84E9 Interrupt Structure Vectors Sources ResetClear Levels HEX 7FFFH 3FFFH Interrupt Vector AddressesInterrupt Vector Area Level Interrupt Control Register Overview Function Description ENABLE/DISABLE Interrupt Instructions EI, DISYSTEM-LEVEL Interrupt Control Registers Interrupt Function Diagram Interrupt Processing Control Points Peripheral Interrupt Control Registers IRQ1 IRQ2 IRQ3 IRQ4 IRQ5 IRQ6 IRQ7 System Mode Register SYMIRQ0 LSB IRQ1 IRQ0 IRQ7 IRQ6 IRQ5 IRQ4 IRQ3 IRQ2 Interrupt Mask Register IMRMSB IRQ0, IRQ1 Interrupt Priority Register IPRGroup a Group B IRQ2, IRQ3, IRQ4 Group C IRQ5, IRQ6, IRQ7 Interrupt Priority Register IPR Interrupt Request Register IRQ Interrupt Request Register IRQ Overview Pending Bits Cleared by the Service RoutineInterrupt Pending Function Types Pending Bits Cleared Automatically by Hardware Interrupt Service Routines Interrupt Source Polling Sequence Generating Interrupt Vector Addresses Nesting of Vectored Interrupts Register Addressing Instruction SETData Types Addressing Modes Lded LDELDC Ldcd Logic Instructions Bit Manipulation Instructions CPU Control Instructions Flags Register Flags System Flags Register Flags Flag Descriptions Instruction SET Notation Instruction Set SymbolsSymbol Description Flag Notation Conventions IML Immediate long addressing mode #data Data =IRR Opcode Quick Reference Opcode MAP Lower Nibble HEX Djnz INC NOP Djnz INC NextR1,R2 R2,R1 Idle Condition Codes Condition Codes Binary Mnemonic Description Flags Set Instruction Descriptions ADC Add with Carry ADC Format ADD AddADD Bytes Cycles Opcode Logical Given R1 = 07H and register 01H = 05H Band BitSrc Opc R1,01H.1 R1 = 06H, register 01H = 05H BCP Bit Compare BCP Hex Dst Bitc Bit ComplementBitc Bitr Bit Reset BITRdst.b Operation dstb ← Bits Bit Set BITSdst.b Operation dstb ← BOR Bit or BOR PC jumps to Skip location Btjrf Bit Test, Jump Relative on FalseBtjrf SKIP,R1.3 If srcb is a 1, then PC ← PC + dst Btjrt Bit Test, Jump Relative on TrueBtjrt Btjrt SKIP,R1.1 Bxor Bit XOR R1,01H.1 R1 = 06H, register 01H 03H @SP ← PCL Call Call ProcedureCall dst Operation SP ← SP-1 @SP ← PCH Operation C ← not C CCF Complement Carry FlagCCF Format Bytes Cycles Opcode Hex 00H Register 00H CLR ClearCLRdst Operation dst ← Opc Dst Examples Given R1 = 07H and register 07H = 0F1H COM ComplementCOMdst Operation dst ← not dst 0F8H Operation dst-src Format Bytes Cycles Opcode Addr Mode Hex Dst SrcCP Compare UGE,SKIP INC Skip Dst,src,RA Cpije Compare, Increment, and Jump on EqualCpije If dst-src = 0, PC Opc Src Dst Cpijne Compare, Increment, and Jump on Non-EqualCpijne Example Given R1 = 02H, R2 = 03H, and register 03H = 04H After DA DA Decimal AdjustDAdst Operation dst ← DA dst ADD ADC 3CH DECdst Operation dst ← dst-1 Contents of the destination operand are decremented by oneDEC Decrement Opc Dst Examples Given R1 = 03H and register 03H = 10H Decw RR0 Decw Decrement WordDecw Loop Decw RR0 DI Disable Interrupts Operation SYM 0 ← Set if the divisor or the quotient = 0 cleared otherwise DIV Divide UnsignedOperation dst ÷ src Set if MSB of the quotient = 1 cleared otherwise SRP #0C0H Djnz R1,LOOP Djnz Decrement and Jump if Non-ZeroDJNZr,dst Operation r ¬ r EI instruction is executed EI Enable InterruptsSYM 0 ← No flags are affected Enter Enter Enter Operation IP ← @SP Exit ExitExit Idle Idle Operation Idle INC 00H INC IncrementINCdst Operation dst ← dst + 0DH INC @R0 0FFH Incw RR0 Incw Increment WordIncw dst Operation dst ← dst + Loop Incw RR0 Flags ← @SP PC ↔ IP Iret Interrupt ReturnIret Flags ← Flags JP Jump Labelw JR C,LABELX JR Jump RelativeHex Dst CcB Cc = 0 to F Opc Dst Src = 0 to F LD LoadDst ← src = 0FFH, R1 = 0AH 0AHLD R0,#LOOPR1 LD #LOOPR0,R1 Dst Examples Given R0 = 06H and general register 00H = 05H LDB Load BitLDB R0,00H.2 07H, register 00H 05H LDC Bytes Cycles Opcode Addr Mode Hex Dst SrcLDC/LDE Load Memory LDE LDC/LDE R0,1104H ← contents of program memory location 1104H = 88HR0,1104H ← contents of external data memory location = 98H Operation dst ← src LDCD/LDED Load Memory and DecrementLdcd dst,src Lded dst,src Ldei LDCI/LDEI Load Memory and IncrementLdci Rr ← rr + Operation rr ← rr LDCPD/LDEPD Load Memory with Pre-DecrementLdcpd dst,src Ldepd dst,src Irr Examples Given R0 = 77H, R6 = 30H, and R7 = 00H Operation rr ← rr + LDCPI/LDEPI Load Memory with Pre-IncrementLdcpi dst,src Ldepi dst,src Irr Examples Given R0 = 7FH, R6 = 21H, and R7 = 0FFH 0FH LDW Load WordLDW RR6,RR4 0EDH Operation dst ← dst × src Mult Multiply UnsignedMult dst,src 00H, @01H Register 00H 00H, register 01H 0C0H Operation PC ← @IP Next NextNext NOP No Operation NOP 00H,#02H Register 00H Or Logical or0BFH Hex Dst Examples POP Pop from StackPOPdst Operation dst ← @SP 0FBH 6FH Popud Pop User Stack DecrementingPopud dst,src Example Given Register 00H = 01H and register 01H = 70H Popui Pop User Stack IncrementingPopui dst,src 0FFH = 0AAH, SPH = 0FFH, SPL = 0FFH Push Push to StackPush src Operation SP ← SP IR ← IR Pushud Push User Stack DecrementingPushud Decremented stack pointer Pushui @00H,01H Pushui Push User Stack IncrementingPushui dst,src Operation IR ← IR + Flags Cleared to RCF Reset Carry FlagRCF Operation PC ← @SP RET ReturnRET Example Given SP RL Rotate Left RLdst Operation C ← dst 00H Register 00H 54H, C = RLC Rotate Left through CarryRLCdst Operation dst 0 ← C RR Rotate Right RRdst Operation C ← dst 00H Register 00H 2AH, C = RRC Rotate Right through CarryRRCdst Operation dst 7 ← C Operation Bank ← SB0 Select BankSB0 SB1 Select Bank SB1 SBC Subtract with Carry 0AH SBC Opc 4DF Example The statement SCF sets the carry flag to SCF Set Carry FlagSCF 00H Register 00H 0CD, C = SRA Shift Right ArithmeticSRAdst SRP0 SRP/SRP0/SRP1 Set Register PointerSRP SRP1 Stop Stop Operation Stop SUB Subtract Opc Dst Examples Given Register 00H Swap Swap NibblesSwap dst Swap 00H Swap @02H R0,@R1 = 0C7H, R1 = 02H, register 02H = 23H, Z = TCM Test Complement under MaskR0,R1 = 0C7H, R1 = 02H, Z = 00H,01H Register 00H 2BH, register 01H 02H, Z = Operation dst and src TM Test under MaskTMdst,src WFI Enable global interruptWFI Wate for Interrupt Opc 4n3F R0,@R1 = 0E4H, R1 = 02H, register 02H = 23H XOR Logical Exclusive orR0,R1 = 0C5H, R1 = 02H 00H,01H Register 00H 29H, register 01H 02H Crystal or Ceramic Oscillator Crystal Oscillator Clock CircuitSystem Clock Circuit S3C84E5 S3C84E9 S3P84E9 Clock Status During POWER-DOWN Modes System Clock Circuit Diagram System Clock Control Register Clkcon S3C84E5/C84E9/P84E9 REV.0 Oscillator Control Register Osccon S3C84E5/C84E9/P84E9 Reset and POWER-DOWN System ResetNormal Mode Reset Operation Overview Reset and POWER-DOWN S3C84E5/C84E9/P84E9 Hardware Reset ValuesDec Hex Timer B control register Converter data registerlow byte S3C84E5/C84E9/P84E9RESET and POWER-DOWNConverter data registerhigh byte Uart baud rate data register high Timer A, 1 interrupt pending registerReset and POWER-DOWNS3C84E5/C84E9/P84E9 Uart baud rate data register low Using Reset to Release Stop Mode POWER-DOWN ModesStop Mode Using an External Interrupt to Release Stop Mode How to Enter into Stop Mode Idle Mode O Ports S3C84E5/C84E9/P84E9 Port Configuration OverviewPort Configuration Options Port Data Registers Port Port 0 Control Register P0CONH/P0CONL P0.1/XTout Configuration Bits P0.3/T1CK1 Configuration BitsP0.2/T1CAP1 Configuration Bits P0.0/XTin Configuration Bits Port 1 Control Register P1CONH, P1CONL P1.5/TXD Configuration BitsP1.4/RXD Configuration Bits P1.1/T1CK0 Configuration Bits P1.3/BZOUT Configuration BitsP1.2/T1OUT0 Configuration Bits P1.0/TAOUT Configuration Bits Port 2 Control Register P2CONH, P2CONL P2.5/INT5 Configuration Bits P2.7/INT7 Configuration BitsP2.6/INT6 Configuration Bits P2.4/INT4 Configuration Bits P2.1/INT1 Configuration Bits P2.3/INT3 Configuration BitsP2.2/INT2 Configuration Bits P2.0/INT0 Configuration Bits P2.5/PND5, Interrupt Pending Bit P2.7/PND7, Interrupt Pending BitP2.6/PND6, Interrupt Pending Bit P2.4/PND4, Interrupt Pending Bit P2.5 External Interrupt INT5 Enable Bit P2.7 External Interrupt INT7 Enable BitP2.6 External Interrupt INT6 Enable Bit P2.4 External Interrupt INT4 Enable Bit P3.5/ADC5 Configuration Bits P3.7/ADC7 Configuration BitsP3.6/ADC6 Configuration Bits P3.4/ADC4 Configuration Bits P3.1/ADC1 Configuration Bits P3.3/ADC3 Configuration BitsP3.2/ADC2 Configuration Bits P3.0/ADC0 Configuration Bits Port 4 Control Register P4CONH, P4CONL P4.3/TBPWM Configuration Bits P4.5 Configuration BitsP4.4 Configuration Bits P4.2/INT10 Configuration Bits P4.0 External Interrupt INT8 Enable Bit P4.2 External Interrupt INT10 Enable BitP4.1 External Interrupt INT9 Enable Bit P4.2/PND10, Interrupt Pending Bit Basic Timer Control Register Btcon Basic TimerBasic Timer BT 10-1 Basic Timer Control Register Btcon 10-2 Oscillation Stabilization Interval Timer Function Basic Timer Function DescriptionWatchdog Timer Function 10-3 OVF DIVMUX 10-4 11-1 11 8-BIT Timer A/BBIT Timer a Pulse Width Modulation Mode Timer a Interrupts IRQ1, Vectors C0H and C2HInterval Timer Function Capture Mode Timer a Control Register Tacon 11-3 Block Diagram 11-4 BIT Timer B 11-5 Timer B Control Register Tbcon 11-6 Timer B Pulse Width Calculations 11-7 11-8 Tbdatal = DFH Tbdatah = 1FHTbdatal = 7FH Tbdatah = 7FH Start DI 0100H Reset addressORG P4CONLH,#03H TBDATAL,# Programming TIP To generate a one pulse signal through P4.3TBDATAH,# Set 40 μs Set any value except 00H Programming TIP Using the Timer a Main Main Routine JRT,MAIN Tbunint Programming TIP Using the Timer B0BEh,TBUNINT 11-12 S3C84E5/C84E9/P84E9 BIT Timer 10,1 12-1 BIT Timer 10,1 S3C84E5/C84E9/P84E9 Timer 10,1 Interrupts IRQ2, Vectors C4H, C6H, C8H and CAHInterval Mode match 12-2 12-3 PWM ModeTimer 10,1 Control Register T1CON0, T1CON1 Timer 10,1 Control Register T1CON0, T1CON1 12-4 Timer A, Timer 10,1 Pending Register Tintpnd 12-5 12-6 T1DATAH0,#00F0h T1DATAH0=00h, T1DATAL0=F0h Programming TIP Using the Timer0C4h,TIM1INT SB0 Main Main Routine JRT,MIAN TIM1INT 13-1 Programming ProcedureUart Uart Control Register Uartcon 13-2 13-3 MSB MS1 MS0 MCE RE TB8 RB8 RIE TIE LSBMS1 MS0 Always Uart Interrupt Pending Register UartpndMust keep always MSB PEN RPE RIP TIP LSB Uart Data Register Udata 13-5 13-6 Uart Baud Rate Data Register BRDATAH, BrdatalBaud Rate Calculations Brdatah Brdatal Decimal Hex 13-8 Tx ControlRx Control Mode 0 Receive Procedure Uart Mode 0 Function DescriptionMode 0 Transmit Procedure 13-9 Mode 1 Receive Procedure Uart Mode 1 Function DescriptionMode 1 Transmit Procedure 13-10 Parity enable mode PEN = Uart Mode 2 Function DescriptionParity disable mode PEN = Mode 2 Transmit Procedure Timing Diagram for Uart Mode 2 Operation 13-12 13-13 Serial Communication for Multiprocessor ConfigurationsSample Protocol for Master/Slave Interaction 13-14 Setup Procedure for Multiprocessor CommunicationsFull-Duplex Multi-S3C84E5/C84E9/P84E9 Interconnect Watch Timer 14-1 WTCON.6 ResetWTCON.7 WTCON.1 Watch Timer Circuit Diagram 14-3 Main Main Routine JRT,MIAN Wtint Programming TIP Using the Watch Timer0CCh,WTINT WTCON,#11111110b Pending clear 15-1 15 A/D ConverterFunction Description Converter Control Register Adcon 15-2 15-3 EOC Addata Internal Reference Voltage LevelsConversion Timing 15-4 15-5 Internal A/D Conversion ProcedureS3C84E5 Programming TIP Configuring A/D Converter LOW Voltage Reset 16-1 16-2 Electrical Data 17-1 Input/Output Capacitance Parameter Symbol Conditions Rating UnitAbsolute Maximum Ratings D.C. Electrical Characteristics VDD = Vlvr 17-4 VDD = 4.5 V to RUN mode MHz CPU clock VDD = Vlvr to 5.5VDD = 4.5 V to 5.5 100 TA = 25C Stop mode VDD = Vlvr to 3.3 Interrupt input A.C. Electrical CharacteristicsPorts NRESET input VDD = 5 180 High, low width Main Oscillator Frequency fOSC1 When released by a reset 216/fWait time TWAIT when released by an interrupt Main Oscillator Clock Stabilization Time tST1 17-7 Subsystem Oscillator crystal Stabilization Time tST2Xtin Data retention Data Retention Supply Voltage in Stop ModeStop mode Supply voltage Data retention Stop mode, Vdddr = 2.0 Supply current Stop Mode Sub Release Timing Initiated by Interrupts 17-9 10. Uart Timing Characteristics in Mode 0 10 MHz 11. A/D Converter Electrical Characteristics Parameter Symbol Test Conditions Min Typ Max Unit 12. LVR Low Voltage Reset Circuit Characteristics 17-12 MIN Mechanical DataMAX 18-1 QFP-1010 18-2 19-1 19 S3P84E9 OTP VersionSdip VPP/TEST 44-QFPSDAT/TBPWM/P4.3 SCLK/INT10/P4.2 19-2 Test MEM Operating Mode CharacteristicsREG 19-4 Sasm Development ToolsShine Sama Assembler OTP Programming Socket Adapter Target BoardsOTP Emulator SMDS2+ or SK-1000 TB84E5/84E9 Target Board 20-3 Idle LED Power Selection Settings for TB84E5/84E9To UserVcc Settings Operating Mode Comments Stop LED PIN DIP Socket TB84E5/84E9 Adapter Cable for 44pin Connector Package 20-6 S3C8- Series Mask ROM Order Form SEC Customer Risk Order Agreement S3C8- Series Request for Production AT Customer RiskRisk Order Information Order Quantity and Delivery Schedule Prom S3C84E5/C84E9 Mask Option Selection FormAttachment Check one Customer Checksum Company Name Signature Engineer

18 MECHANICAL DATA

OVERVIEW

42-SDIP-600

MAX

MIN

Figure 18-1. 42-SDIP-600 Package Dimensions

18-1