Samsung S3C84E5 user manual DA Decimal Adjust, DAdst Operation dst ← DA dst, After DA, Add Adc

S3C84E5/C84E9/P84E9 INSTRUCTION SET

DA — Decimal Adjust

DAdst

Operation: dst ← DA dst

The destination operand is adjusted to form two 4-bit BCD digits following an addition or subtraction operation. For addition (ADD, ADC) or subtraction (SUB, SBC), the following table indicates the operation performed (The operation is undefined if the destination operand is not the result of a valid addition or subtraction of BCD digits):

	Instruction	Carry	Bits 4–7	H Flag	Bits 0–3	Number Added		Carry
		Before DA	Value (Hex)	Before DA	Value (Hex)	to Byte		After DA
		0	0–9	0	0–9		00	0
		0	0–8	0	A–F		06	0
		0	0–9	1	0–3		06	0
	ADD	0	A–F	0	0–9		60	1
	ADC	0	9–F	0	A–F		66	1
		0	A–F	1	0–3		66	1
		1	0–2	0	0–9		60	1
		1	0–2	0	A–F		66	1
		1	0–3	1	0–3		66	1
		0	0–9	0	0–9	00	= – 00	0
	SUB	0	0–8	1	6–F	FA = – 06		0
	SBC	1	7–F	0	0–9	A0 = – 60		1
		1	6–F	1	6–F	9A	= – 66	1
Flags:		C: Set if there was a carry from the most significant bit; cleared otherwise (see table).

Z:Set if result is "0"; cleared otherwise.

S:Set if result bit 7 is set; cleared otherwise.

V:Undefined.

D:Unaffected.

H:Unaffected.

Format:

Bytes Cycles Opcode	Addr Mode
(Hex)	dst

opc

dst

2	4	40	R
	4	41	IR

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