Samsung S3C84E5 user manual MSB MS1 MS0 MCE RE TB8 RB8 RIE TIE LSB, 13-3

S3C84E5/C84E9/P84E9 UART

UART Control Register (UARTCON)

F6H, Set1, Bank 0, R/W, Reset Value: 00H

MSB MS1 MS0 MCE RE TB8 RB8 RIE TIE

LSB

Operating mode and baud rate selection bits (see table below)

Multiprocessor communication (1) enable bit (mode 2 only):

0 = Disable

1 = Enable

Serial data receive enable bit: 0 = Disable

1 = Enable

If parity disable mode (PEN = 0),

location of the 9th data bit to be transmitted in UART mode 2 ("0" or "1").

If parity enable mode (PEN = 1),

Even/odd parity selection bit for transmit data in UART mode 2;

0 : Even parity bit generation for transmit data

1 : Odd parity bit generation for transmit data

Transmit interrupt enable bit:

0 = Disable

1 = Enable

Received interrupt enable bit: 0 = Disable

1 = Enable

If parity disable mode (PEN = 0),

location of the 9th data bit that was received in UART mode 2 ("0" or "1").

If parity enable mode (PEN = 1),

Even/odd parity selection bit for receive data in UART mode 2.

0 : Even parity check for the received data

1 : Odd parity check for the received data

			(2)
MS1 MS0		Mode	Description	Baud Rate
0	0	0	Shift register	fxx / (16 x (16bit BRDATA + 1))
0	1	1	8-bit UART	fxx / (16 x (16bit BRDATA + 1))
1	x	2	9-bit UART	fxx / (16 x (16bit BRDATA + 1))

NOTES:

1.In mode 2, if the UARTCON.5 bit is set to "1" then the receive interrupt will not be activated if the received 9th data bit is "0". In mode 1, if UARTCON.5 = "1" then the receive interrut will not be activated if a valid stop bit was not received.

2.The descriptions for 8-bit and 9-bit UART mode do not include start and stop bits for serial data receive and transmit.

3.Parity enable bits, PEN, is located in the UARTPND register at address F4H.

4.Parity enable and parity error check can be available in 9-bit UART mode (Mode 2) only.

Figure 13-1. UART Control Register (UARTCON)

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