CONTROL REGISTERS S3C84E5/C84E9/P84E9
4-38
UARTCON — UART Control Register F6H Set 1, Bank 0
Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0
Reset Value 0 0 0 0 0 0 0 0
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
.7–.6 Operating Mode and Baud Rate Selection Bits
0 0 Mode 0: Shift Register [fxx/(16 × (16-bit BRDATA + 1))]
0 1 Mode 1: 8-bit UART [fxx/(16 × (16-bit BRDATA + 1))]
1 X Mode 2: 9-bit UART [fxx/(16 × (16-bit BRDATA + 1))]
.5 Multiprocessor Communication (1) Enable Bit (for mode 2 only)
0 Disable
1 Enable
.4 Serial Data Receive Enable Bit
0 Disable
1 Enable
.3 If Parity disable mode (PEN = 0),
location of the 9th data bit to be transmitted in UART mode 2 ("0" or "1").
If Parity enable mode (PEN = 1),
even/odd parity selection bit for transmit data in UART mode 2.
0: Even parity bit generation for transmit data
1: Odd parity bit generation for transmit data
.2 If Parity disable (PEN = 0),
location of the 9th data bit that was received in UART mode 2 ("0" or "1").
If Parity enable mode (PEN = 1),
even/odd parity selection bit for receive data in UART mode 2.
0: Even parity check for the received data
1: Odd parity check for the received data
A result of parity error will be saved in RPE bit of the UARTPND register after parity
checking of the received data.
.1 Receive Interrupt Enable Bit
0 Disable receive interrupt
1 Enable receive interrupt
.0 Transmit Interrupt Enable Bit
0 Disable transmit interrupt
1 Enable transmit Interrupt