Samsung S3C84E5 Uartcon Uart Control Register F6H Set 1, Bank, Serial Data Receive Enable Bit

CONTROL REGISTERSS3C84E5/C84E9/P84E9

UARTCON — UART Control Register F6H Set 1, Bank 0

Bit Identifier

Reset Value

Read/Write

.7	.6	.5	.4	.3	.2	.1	.0
0	0	0	0	0	0	0	0
R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W

.7–.6	Operating Mode and Baud Rate Selection Bits
	0	0	Mode 0: Shift Register [fxx/(16 × (16-bit BRDATA + 1))]
	0	1	Mode 1: 8-bit UART [fxx/(16 × (16-bit BRDATA + 1))]
	1	X	Mode 2: 9-bit UART [fxx/(16 × (16-bit BRDATA + 1))]
.5	Multiprocessor Communication (1) Enable Bit (for mode 2 only)
	0	Disable
	1	Enable
.4	Serial Data Receive Enable Bit
	0	Disable
	1	Enable

.3

If Parity disable mode (PEN = 0),

location of the 9th data bit to be transmitted in UART mode 2 ("0" or "1"). If Parity enable mode (PEN = 1),

even/odd parity selection bit for transmit data in UART mode 2.

0:Even parity bit generation for transmit data

1:Odd parity bit generation for transmit data

.2

.1

.0

If Parity disable (PEN = 0),

location of the 9th data bit that was received in UART mode 2 ("0" or "1"). If Parity enable mode (PEN = 1),

even/odd parity selection bit for receive data in UART mode 2.

0:Even parity check for the received data

1:Odd parity check for the received data

A result of parity error will be saved in RPE bit of the UARTPND register after parity checking of the received data.

Receive Interrupt Enable Bit

0Disable receive interrupt

1Enable receive interrupt

Transmit Interrupt Enable Bit

0Disable transmit interrupt

1Enable transmit Interrupt

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