Interrupt Priority Register IPR | Samsung S3C84E5 specs

S3C84E5/C84E9/P84E9	INTERRUPT STRUCTURE

MSB

Interrupt Priority Register (IPR)

FFH, Set 1, Bank 0, R/W

.7	.6	.5	.4	.3	.2	.1	.0

LSB

Group priority:


D7	D4	D1
0	0	0	= Undefined
0	0	1	= B > C > A
0	1	0	= A > B >C

01 1 = B > A > C

10 0 = C > A > B

1 0 1 = C > B > A

11 0 = A > C > B

11 1 = Undefined

Group A

0 = IRQ0 > IRQ1

1 = IRQ1 > IRQ0

Group B

0 = IRQ2 > (IRQ3, IRQ4)

1 = (IRQ3, IRQ4) > IRQ2

Subgroup B

0 = IRQ3 > IRQ4

1 = IRQ4 > IRQ3

Group C

0 = IRQ5 > (IRQ6, IRQ7)

1 = (IRQ6, IRQ7) > IRQ5

Subgroup C

0 = IRQ6 > IRQ7

1 = IRQ7 > IRQ6

Figure 5-8. Interrupt Priority Register (IPR)

5-13

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Image 123

Samsung S3C84E5 user manual Interrupt Priority Register IPR

Contents

Page Errata VER FeaturesLow Voltage Reset Built-in Reset circuit LVR Reset VDDBGR Parameter Symbol Conditions Min Typ Max Unit D.C. Electrical Characteristics Pull-up resistor VDD = 4.5V to RUN mode MHz CPU clock VDD = Vlvr to 5.5 Sub Oscillator Frequency A.C. Electrical CharacteristicsMain Oscillator Frequency Main Oscillator Clock Stabilization TimePAGE Oscillator Test Condition Min Typ Max Unit Data Retention Supply Voltage in Stop Mode10. Uart Timing Characteristics in Mode 0 Parameter Symbol Min Typ Max Unit Operating Voltage RangePAGE 11. A/D Converter Electrical Characteristics12. LVR Low Voltage Reset Circuit Characteristics Comparison of S3P84E9 and S3C84E5/C84E9 Features S3C84E5/C84E9/P84E9 Important Notice Part Programming Model UartIii Table of Contents Overview Chapter Interrupt Structure Vii Part II Hardware Descriptions Viii Chapter HEX2ROM Title Number List of Figures Xii 10-210-4 11-8 13-7 12-412-5 13-3 17-11 17-2 Xvi Chapter Converter Configuring A/D Converter 15-6 Chapter Bit Timer A/BChapter Bit Timer 10,1 Chapter Watch Timer Register Full Register Name Identifier Number Instruction Full Register Name Mnemonic Number LDCPD/LDEPD LDC/LDELDCD/LDED LDCI/LDEI Product Overview S3C8-SERIES MicrocontrollersS3C84E5/C84E9/P84E9 Microcontroller CPU Features S3C84E5/C84E9/P84E9 Block Diagram Block Diagram 44-QFP NRESETPIN Assignment Top View Sdip S3C84E5S3C84E9 S3P84E9 Type Description Number Pins PIN DescriptionsS3C84E5/C84E9/P84E9 Pin Descriptions Circuit Share Test INT0-INT10AVREF, Avss BUZ PIN Circuits Pin Circuit Type B nRESET Pin Circuit Type D P0.2-P0.7, P1, P4.3-P4.5 Pin Circuit Type E P3 Overview Address Spaces Program Memory ROM HEX0FFH 590 Register ArchitectureS3C84E5/C84E9/P84E9 Register Type Summary Number of Bytes Total Addressable Bytes Page01 PagePage00 Set Set1 Bank MSB LSB Register page Pointer PP RAMCL1 CLR SRPRAMCL0 CLR Djnz R0,RAMCL0 CLR Register SET C0H BFH Prime Register SpaceFFH F0H E0H D0H C0H Set Bank Working Registers F8HF7H SRP0 Using the Register PointersProgramming TIP Setting the Register Pointers SRP1 + R2 + C #80H RP0 ← 80HR0,R1 ← R0 + R1 R0,R2 Bit Register Pair Register Addressing Prime Registers FFH E0H D0H C0H BFHControl Registers System Register Pointers E0H D0H C0H BFH Common Working Register Area C0H-CFHRP1 → C8H-CFH FFH F0H BIT Working Register Addressing Programming TIP Addressing the Common Working Register AreaExamples Example R6 Opcode RP0 RP1 13 -Bit Working Register Addressing 14 -Bit Working Register Addressing Example High Address System and User StackStack Operations Stack Pointers SPL, SPH POP RP1 SPL,#0FFH SPL ← FFHPush RP0 Push RP1 Addressing Modes Operand Register Addressing Mode ROpcode DEC Cntr Indirect Register Addressing Mode IR Address@SHIFT Indirect Register Addressing Mode Register PairCall @RR2 JP @RR2 Indirect Working Register Addressing to Register File LDE LCD Index Indexed Addressing Mode Indexed Addressing Mode OffsetLDC Indexed Addressing to Program or Data Memory 10. Direct Addressing for Load Instructions Direct Address Mode DA Direct Address Mode JOB1Call Display Call #40H Indirect Address Mode IA ULT,$+OFFSET Relative Address Mode RA Immediate Mode IM Operand OpcodeLD R0,#0AAH Set 1 Registers Register Name Mnemonic Decimal Hex Control Registers Set 1, Bank 0 Registers Register Name Mnemonic Decimal Hex Set 1, Bank 1 Registers Register Name Mnemonic Decimal Hex Sign Flag S Bit Identifier Reset Value Read/Write Bit AddressingMode Carry Flag C Zero Flag Z Adcon A/D Converter Control Register F7H Set 1, Bank D3H Btcon Basic Timer Control Register Fxx/2 Clkcon System Clock Control RegisterD4H CPU Clock System Clock Selection Bits note D5H Flags System Flags Register DDH IMR Interrupt Mask Register DBH IPH Instruction Pointer High ByteDAH IPL Instruction Pointer Low Byte FFH IPR Interrupt Priority Register DCH IRQ Interrupt Request Register Sub System Oscillator Control Bit Osccon Oscillator Control Register FBH Set 1, BankSub-system Oscillator Driving Ability Control Bit Main System Oscillator Control Bit P0.4/T1OUT1 Configuration Bits P0.7/TACAP Configuration BitsP0.6/TACK Configuration Bits P0.5/T1CAP0 Configuration Bits P0.0/XTin Configuration Bits P0.3/T1CK1 Configuration BitsP0.2/T1CAP1 Configuration Bits P0.1/XTout Configuration Bits P1.5/TXD Configuration Bits P1.4/RXD Configuration BitsP1CONH Port 1 Control Register High Byte E8H Set 1, Bank P1.0/TAOUT Configuration Bits P1.3/BZOUT Configuration BitsP1.2/T1OUT0 Configuration Bits P1.1/T1CK0 Configuration Bits P2.5/ INT5 P2CONH Port 2 Control Register High Byte EAH Set 1, BankP2.7/INT7 P2.6/ INT6 P2.1/INT1 P2CONL Port 2 Control Register Low Byte EBH Set 1, BankP2.3/INT3 P2.2/INT2 ECH P2INT Port 2 Interrupt Control Register EDH P2INTPND Port 2 Interrupt Pending Register 2P3.5/ADC5 P3CONH Port 3 Control Register High Byte EEH Set 1, BankP3.7/ADC7 4P3.6/ADC6 3P3.1/ADC1 P3CONL Port 3 Control Register Low Byte EFH Set 1, BankP3.3/ADC3 4P3.2/ADC2 P4.4 Input mode Push-pull output modeP4CONH Port 4 Control Register High Byte F0H Set 1, Bank P4.5 P4.1/INT9 P4CONL Port 4 Control Register Low Byte F1H Set 1, BankP4.3/TBPWM P4.2/INT10 P4INT Port 4 Interrupt Control Register P4.2 External Interrupt INT10 Enable BitP4.1 External Interrupt INT9 Enable Bit P4.0 External Interrupt INT8 Enable Bit P4.1/PND9 Interrupt Pending Bit P4INTPND Port 4 Interrupt Pending RegisterF3H P4.2/PND10 Interrupt Pending Bit Source Register Page Selection Bits PP Register Page PointerDFH Destination Register Page Selection Bits D7H RP0 Register PointerD6H RP1 Register Pointer SPL Stack Pointer Low Byte SPH Stack Pointer High ByteD8H Set Stop Control Bits Stpcon Stop Control Register E5H Set 1, Bank DEH SYM System Mode RegisterFast Interrupt Enable Bit Global Interrupt Enable Bit note T1CON0 Timer 10 Control Register E8H Set 1, Bank T1CON1 Timer 11 Control Register E9H Set 1, Bank Tacon Timer a Control Register E1H Set 1, Bank D0H Tbcon Timer B Control Register Tintpnd Timer A, Timer 1 Interrupt Pending Register E0H Transmit Interrupt Enable Bit Multiprocessor Communication 1 Enable Bit for mode 2 onlySerial Data Receive Enable Bit Receive Interrupt Enable Bit Control Register Uartpnd Uart Pending and parity control F4H Set 1, Bank Wtcon Watch Timer Control Register FAH Set 1, Bank Sources Interrupt StructureLevels Vectors Levels Type 1 IRQn Type 2 IRQn Type 3 IRQn Vectors Sources Interrupt Types S3C84E5/C84E9/P84E9 Interrupt Structure Levels Vectors Sources ResetClear Interrupt Vector Addresses Interrupt Vector AreaHEX 7FFFH 3FFFH Level ENABLE/DISABLE Interrupt Instructions EI, DI SYSTEM-LEVEL Interrupt Control RegistersInterrupt Control Register Overview Function Description Interrupt Processing Control Points Interrupt Function Diagram Peripheral Interrupt Control Registers System Mode Register SYM IRQ0IRQ1 IRQ2 IRQ3 IRQ4 IRQ5 IRQ6 IRQ7 Interrupt Mask Register IMR MSBLSB IRQ1 IRQ0 IRQ7 IRQ6 IRQ5 IRQ4 IRQ3 IRQ2 Group B IRQ2, IRQ3, IRQ4 Group C IRQ5, IRQ6, IRQ7 Interrupt Priority Register IPRGroup a IRQ0, IRQ1 Interrupt Priority Register IPR Interrupt Request Register IRQ Interrupt Request Register IRQ Pending Bits Cleared Automatically by Hardware Pending Bits Cleared by the Service RoutineInterrupt Pending Function Types Overview Interrupt Source Polling Sequence Interrupt Service Routines Nesting of Vectored Interrupts Generating Interrupt Vector Addresses Addressing Modes Instruction SETData Types Register Addressing Ldcd LDELDC Lded Logic Instructions Bit Manipulation Instructions CPU Control Instructions System Flags Register Flags Flags Register Flags Flag Descriptions Flag Notation Conventions Instruction Set SymbolsSymbol Description Instruction SET Notation Immediate long addressing mode #data Data = IRRIML Opcode MAP Lower Nibble HEX Opcode Quick Reference Idle Djnz INC NextR1,R2 R2,R1 Djnz INC NOP Condition Codes Binary Mnemonic Description Flags Set Condition Codes Instruction Descriptions ADC ADC Add with Carry Bytes Cycles Opcode ADD AddADD Format Logical R1,01H.1 R1 = 06H, register 01H = 05H Band BitSrc Opc Given R1 = 07H and register 01H = 05H BCP BCP Bit Compare Bitc Bit Complement BitcHex Dst BITRdst.b Operation dstb ← Bitr Bit Reset BITSdst.b Operation dstb ← Bits Bit Set BOR BOR Bit or Btjrf Bit Test, Jump Relative on False Btjrf SKIP,R1.3PC jumps to Skip location Btjrt SKIP,R1.1 Btjrt Bit Test, Jump Relative on TrueBtjrt If srcb is a 1, then PC ← PC + dst R1,01H.1 R1 = 06H, register 01H 03H Bxor Bit XOR @SP ← PCH Call Call ProcedureCall dst Operation SP ← SP-1 @SP ← PCL Format Bytes Cycles Opcode Hex CCF Complement Carry FlagCCF Operation C ← not C CLR Clear CLRdst Operation dst ←00H Register 00H 0F8H COM ComplementCOMdst Operation dst ← not dst Opc Dst Examples Given R1 = 07H and register 07H = 0F1H UGE,SKIP INC Skip Format Bytes Cycles Opcode Addr Mode Hex Dst SrcCP Compare Operation dst-src If dst-src = 0, PC Cpije Compare, Increment, and Jump on EqualCpije Dst,src,RA Example Given R1 = 02H, R2 = 03H, and register 03H = 04H Cpijne Compare, Increment, and Jump on Non-EqualCpijne Opc Src Dst ADD ADC DA Decimal AdjustDAdst Operation dst ← DA dst After DA 3CH Opc Dst Examples Given R1 = 03H and register 03H = 10H Contents of the destination operand are decremented by oneDEC Decrement DECdst Operation dst ← dst-1 Loop Decw RR0 Decw Decrement WordDecw Decw RR0 Operation SYM 0 ← DI Disable Interrupts Set if MSB of the quotient = 1 cleared otherwise DIV Divide UnsignedOperation dst ÷ src Set if the divisor or the quotient = 0 cleared otherwise Djnz Decrement and Jump if Non-Zero DJNZr,dst Operation r ¬ rSRP #0C0H Djnz R1,LOOP No flags are affected EI Enable InterruptsSYM 0 ← EI instruction is executed Enter Enter Enter Exit Exit ExitOperation IP ← @SP Idle Idle Idle Operation 0DH INC @R0 INC IncrementINCdst Operation dst ← dst + INC 00H Loop Incw RR0 Incw Increment WordIncw dst Operation dst ← dst + 0FFH Incw RR0 Flags ← Flags Iret Interrupt ReturnIret Flags ← @SP PC ↔ IP Labelw JP Jump JR Jump Relative Hex Dst CcB Cc = 0 to FJR C,LABELX LD Load Dst ← srcOpc Dst Src = 0 to F LD #LOOPR0,R1 0AHLD R0,#LOOPR1 = 0FFH, R1 = 0AH R0,00H.2 07H, register 00H 05H LDB Load BitLDB Dst Examples Given R0 = 06H and general register 00H = 05H LDE Bytes Cycles Opcode Addr Mode Hex Dst SrcLDC/LDE Load Memory LDC R0,1104H ← contents of program memory location 1104H = 88H R0,1104H ← contents of external data memory location = 98HLDC/LDE LDCD/LDED Load Memory and Decrement Ldcd dst,src Lded dst,srcOperation dst ← src Rr ← rr + LDCI/LDEI Load Memory and IncrementLdci Ldei Irr Examples Given R0 = 77H, R6 = 30H, and R7 = 00H LDCPD/LDEPD Load Memory with Pre-DecrementLdcpd dst,src Ldepd dst,src Operation rr ← rr Irr Examples Given R0 = 7FH, R6 = 21H, and R7 = 0FFH LDCPI/LDEPI Load Memory with Pre-IncrementLdcpi dst,src Ldepi dst,src Operation rr ← rr + 0EDH LDW Load WordLDW RR6,RR4 0FH 00H, @01H Register 00H 00H, register 01H 0C0H Mult Multiply UnsignedMult dst,src Operation dst ← dst × src Next Next NextOperation PC ← @IP NOP NOP No Operation Or Logical or 0BFH00H,#02H Register 00H 0FBH POP Pop from StackPOPdst Operation dst ← @SP Hex Dst Examples Popud Pop User Stack Decrementing Popud dst,src6FH Popui Pop User Stack Incrementing Popui dst,srcExample Given Register 00H = 01H and register 01H = 70H Push Push to Stack Push src Operation SP ← SP0FFH = 0AAH, SPH = 0FFH, SPL = 0FFH Decremented stack pointer Pushud Push User Stack DecrementingPushud IR ← IR Pushui Push User Stack Incrementing Pushui dst,src Operation IR ← IR +Pushui @00H,01H RCF Reset Carry Flag RCFFlags Cleared to Example Given SP RET ReturnRET Operation PC ← @SP RLdst Operation C ← dst RL Rotate Left RLC Rotate Left through Carry RLCdst Operation dst 0 ← C00H Register 00H 54H, C = RRdst Operation C ← dst RR Rotate Right RRC Rotate Right through Carry RRCdst Operation dst 7 ← C00H Register 00H 2AH, C = SB0 Select Bank SB0Operation Bank ← SB1 SB1 Select Bank 0AH SBC SBC Subtract with Carry SCF Set Carry Flag SCFOpc 4DF Example The statement SCF sets the carry flag to SRA Shift Right Arithmetic SRAdst00H Register 00H 0CD, C = SRP1 SRP/SRP0/SRP1 Set Register PointerSRP SRP0 Stop Stop Stop Operation SUB Subtract Swap 00H Swap @02H Swap Swap NibblesSwap dst Opc Dst Examples Given Register 00H 00H,01H Register 00H 2BH, register 01H 02H, Z = TCM Test Complement under MaskR0,R1 = 0C7H, R1 = 02H, Z = R0,@R1 = 0C7H, R1 = 02H, register 02H = 23H, Z = TM Test under Mask TMdst,srcOperation dst and src Opc 4n3F Enable global interruptWFI Wate for Interrupt WFI 00H,01H Register 00H 29H, register 01H 02H XOR Logical Exclusive orR0,R1 = 0C5H, R1 = 02H R0,@R1 = 0E4H, R1 = 02H, register 02H = 23H S3C84E5 S3C84E9 S3P84E9 Clock CircuitSystem Clock Circuit Crystal or Ceramic Oscillator Crystal Oscillator System Clock Circuit Diagram Clock Status During POWER-DOWN Modes S3C84E5/C84E9/P84E9 REV.0 System Clock Control Register Clkcon Oscillator Control Register Osccon Overview System ResetNormal Mode Reset Operation S3C84E5/C84E9/P84E9 Reset and POWER-DOWN Hardware Reset Values Dec Hex Timer B control registerReset and POWER-DOWN S3C84E5/C84E9/P84E9 S3C84E5/C84E9/P84E9RESET and POWER-DOWN Converter data registerhigh byteConverter data registerlow byte Uart baud rate data register low Timer A, 1 interrupt pending registerReset and POWER-DOWNS3C84E5/C84E9/P84E9 Uart baud rate data register high Using an External Interrupt to Release Stop Mode POWER-DOWN ModesStop Mode Using Reset to Release Stop Mode Idle Mode How to Enter into Stop Mode S3C84E5/C84E9/P84E9 Port Configuration Overview Port Configuration OptionsO Ports Port Data Registers Port 0 Control Register P0CONH/P0CONL Port P0.0/XTin Configuration Bits P0.3/T1CK1 Configuration BitsP0.2/T1CAP1 Configuration Bits P0.1/XTout Configuration Bits P1.5/TXD Configuration Bits P1.4/RXD Configuration BitsPort 1 Control Register P1CONH, P1CONL P1.0/TAOUT Configuration Bits P1.3/BZOUT Configuration BitsP1.2/T1OUT0 Configuration Bits P1.1/T1CK0 Configuration Bits Port 2 Control Register P2CONH, P2CONL P2.4/INT4 Configuration Bits P2.7/INT7 Configuration BitsP2.6/INT6 Configuration Bits P2.5/INT5 Configuration Bits P2.0/INT0 Configuration Bits P2.3/INT3 Configuration BitsP2.2/INT2 Configuration Bits P2.1/INT1 Configuration Bits P2.4/PND4, Interrupt Pending Bit P2.7/PND7, Interrupt Pending BitP2.6/PND6, Interrupt Pending Bit P2.5/PND5, Interrupt Pending Bit P2.4 External Interrupt INT4 Enable Bit P2.7 External Interrupt INT7 Enable BitP2.6 External Interrupt INT6 Enable Bit P2.5 External Interrupt INT5 Enable Bit P3.4/ADC4 Configuration Bits P3.7/ADC7 Configuration BitsP3.6/ADC6 Configuration Bits P3.5/ADC5 Configuration Bits P3.0/ADC0 Configuration Bits P3.3/ADC3 Configuration BitsP3.2/ADC2 Configuration Bits P3.1/ADC1 Configuration Bits Port 4 Control Register P4CONH, P4CONL P4.2/INT10 Configuration Bits P4.5 Configuration BitsP4.4 Configuration Bits P4.3/TBPWM Configuration Bits P4.2/PND10, Interrupt Pending Bit P4.2 External Interrupt INT10 Enable BitP4.1 External Interrupt INT9 Enable Bit P4.0 External Interrupt INT8 Enable Bit 10-1 Basic TimerBasic Timer BT Basic Timer Control Register Btcon 10-2 Basic Timer Control Register Btcon 10-3 Basic Timer Function DescriptionWatchdog Timer Function Oscillation Stabilization Interval Timer Function 10-4 DIVMUX OVF 11 8-BIT Timer A/B BIT Timer a11-1 Capture Mode Timer a Interrupts IRQ1, Vectors C0H and C2HInterval Timer Function Pulse Width Modulation Mode 11-3 Timer a Control Register Tacon 11-4 Block Diagram 11-5 BIT Timer B 11-6 Timer B Control Register Tbcon 11-7 Timer B Pulse Width Calculations Tbdatal = DFH Tbdatah = 1FH Tbdatal = 7FH Tbdatah = 7FH11-8 P4CONLH,#03H 0100H Reset addressORG Start DI Set any value except 00H Programming TIP To generate a one pulse signal through P4.3TBDATAH,# Set 40 μs TBDATAL,# Programming TIP Using the Timer a 11-12 Programming TIP Using the Timer B0BEh,TBUNINT Main Main Routine JRT,MAIN Tbunint 12-1 S3C84E5/C84E9/P84E9 BIT Timer 10,1 12-2 Timer 10,1 Interrupts IRQ2, Vectors C4H, C6H, C8H and CAHInterval Mode match BIT Timer 10,1 S3C84E5/C84E9/P84E9 PWM Mode Timer 10,1 Control Register T1CON0, T1CON112-3 12-4 Timer 10,1 Control Register T1CON0, T1CON1 12-5 Timer A, Timer 10,1 Pending Register Tintpnd 12-6 SB0 Main Main Routine JRT,MIAN TIM1INT Programming TIP Using the Timer0C4h,TIM1INT T1DATAH0,#00F0h T1DATAH0=00h, T1DATAL0=F0h Programming Procedure Uart13-1 13-2 Uart Control Register Uartcon MSB MS1 MS0 MCE RE TB8 RB8 RIE TIE LSB MS1 MS013-3 MSB PEN RPE RIP TIP LSB Uart Interrupt Pending Register UartpndMust keep always Always 13-5 Uart Data Register Udata Uart Baud Rate Data Register BRDATAH, Brdatal Baud Rate Calculations13-6 Decimal Hex Brdatah Brdatal Tx Control Rx Control13-8 13-9 Uart Mode 0 Function DescriptionMode 0 Transmit Procedure Mode 0 Receive Procedure 13-10 Uart Mode 1 Function DescriptionMode 1 Transmit Procedure Mode 1 Receive Procedure Mode 2 Transmit Procedure Uart Mode 2 Function DescriptionParity disable mode PEN = Parity enable mode PEN = 13-12 Timing Diagram for Uart Mode 2 Operation Serial Communication for Multiprocessor Configurations Sample Protocol for Master/Slave Interaction13-13 Setup Procedure for Multiprocessor Communications Full-Duplex Multi-S3C84E5/C84E9/P84E9 Interconnect13-14 14-1 Watch Timer WTCON.1 ResetWTCON.7 WTCON.6 14-3 Watch Timer Circuit Diagram WTCON,#11111110b Pending clear Programming TIP Using the Watch Timer0CCh,WTINT Main Main Routine JRT,MIAN Wtint 15 A/D Converter Function Description15-1 15-2 Converter Control Register Adcon 15-3 15-4 Internal Reference Voltage LevelsConversion Timing EOC Addata Internal A/D Conversion Procedure S3C84E515-5 Programming TIP Configuring A/D Converter 16-1 LOW Voltage Reset 16-2 17-1 Electrical Data Parameter Symbol Conditions Rating Unit Absolute Maximum RatingsInput/Output Capacitance VDD = Vlvr D.C. Electrical Characteristics VDD = 4.5 V to RUN mode MHz CPU clock VDD = Vlvr to 5.5 VDD = 4.5 V to 5.5 100 TA = 25C Stop mode VDD = Vlvr to 3.317-4 VDD = 5 180 High, low width A.C. Electrical CharacteristicsPorts NRESET input Interrupt input Main Oscillator Clock Stabilization Time tST1 When released by a reset 216/fWait time TWAIT when released by an interrupt Main Oscillator Frequency fOSC1 Subsystem Oscillator crystal Stabilization Time tST2 Xtin17-7 Stop mode, Vdddr = 2.0 Supply current Data Retention Supply Voltage in Stop ModeStop mode Supply voltage Data retention Data retention 17-9 Stop Mode Sub Release Timing Initiated by Interrupts 10. Uart Timing Characteristics in Mode 0 10 MHz Parameter Symbol Test Conditions Min Typ Max Unit 11. A/D Converter Electrical Characteristics 17-12 12. LVR Low Voltage Reset Circuit Characteristics 18-1 Mechanical DataMAX MIN 18-2 QFP-1010 19 S3P84E9 OTP Version Sdip19-1 19-2 44-QFPSDAT/TBPWM/P4.3 SCLK/INT10/P4.2 VPP/TEST Operating Mode Characteristics REGTest MEM 19-4 Sama Assembler Development ToolsShine Sasm Emulator SMDS2+ or SK-1000 Target BoardsOTP OTP Programming Socket Adapter 20-3 TB84E5/84E9 Target Board Stop LED Power Selection Settings for TB84E5/84E9To UserVcc Settings Operating Mode Comments Idle LED PIN DIP Socket 20-6 TB84E5/84E9 Adapter Cable for 44pin Connector Package SEC S3C8- Series Mask ROM Order Form Order Quantity and Delivery Schedule S3C8- Series Request for Production AT Customer RiskRisk Order Information Customer Risk Order Agreement Customer Checksum Company Name Signature Engineer S3C84E5/C84E9 Mask Option Selection FormAttachment Check one Prom