Main
USER'S MANUAL ERRATA
ERRATA (VER 1.1)
1. Features (PAGE 1-2)
2. Low Voltage Reset (PAGE 16-1)
3. Low Voltage Reset (PAGE 16-2)
Figure 16-1. Low Voltage Reset Circuit
4. Table 17-3. D.C. Electrical Characteristics (PAGE 17-3)
5. Table 17-3. D.C. Electrical Characteristics (PAGE 17-4)
6. Table 17-4. A.C. Electrical Characteristics (PAGE 17-5)
7. Table 17-5. Main Oscillator Frequency (PAGE 17-6)
8. Table 17-6. Main Oscillator Clock Stabilization Time(PAGE 17-6)
9. Table 17-7. Sub Oscillator Frequency (PAGE 17-7)
10. Table 17-8. Subsystem Oscillator (crystal) Stabilization Time (PAGE 17-7)
11. Table 17-9. Data Retention Supply Voltage in Stop Mode (PAGE 17-8)
12. Table 17-10. UART Timing Characteristics in Mode 0 (PAGE 17-10)
13. Table 17-11. A/D Converter Electrical Characteristics (PAGE 17-11)
14. Table 17-12. LVR (Low Voltage Reset) Circuit Characteristics (PAGE 17-12)
15. Figure 17-8. Operating Voltage Range(PAGE 17-12)
16. Table 19-2. Comparison of S3P84E9 and S3C84E5/C84E9 Features (PAGE 17-12)
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Important Notice
Preface
Table of Contents
Part I Programming Model
Chapter 1 Product Overview
Chapter 2 Address Spaces
Chapter 3 Addressing Modes
Chapter 4 Control Registers
Chapter 5 Interrupt Structure
Chapter 6 Instruction Set
Part II Hardware Descriptions
Chapter 7 Clock Circuit
Chapter 8 RESET and Power-Down
Chapter 9 I/O Ports
Chapter 10 Basic Timer
Chapter 11 8-bit Timer A/B
Chapter 12 16-bit Timer 1(0, 1)
Chapter 13 UART
Chapter 14 Watch Timer
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List of Figures
List of Figures (Continued)
List of Figures (Concluded)
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List of Tables
List of Programming Tips
List of Register Descriptions
List of Instruction Descriptions
List of Instruction Descriptions (Continued)
1
S3C8-SERIES MICROCONTROLLERS
S3C84E5/C84E9/P84E9 MICROCONTROLLER
FEATURES
S3C84E5/C84E9/P84E9 PRODUCT OVERVIEW
1-3
BLOCK DIAGRAM
Watch Timer
Xout, XTout
Figure 1-1. S3C84E5/C84E9/P84E9 Block Diagram
PRODUCT OVERVIEW S3C84E5/C84E9/P84E9
PIN ASSIGNMENT
S3C84E5 S3C84E9 S3P84E9
Top View (44-QFP)
Figure 1-2. S3C84E5/C84E9/P84E9 Pin Assignment (44-pin QFP)
S3C84E5/C84E9/P84E9 PRODUCT OVERVIEW
PIN ASSIGNMENT
S3C84E5 S3C84E9 S3P84E9
Top View (42-SDIP)
Figure 1-3. S3C84E5/C84E9/P84E9 Pin Assignment (42-pin SDIP)
PIN DESCRIPTIONS
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PIN CIRCUITS
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Figure 1-8. Pin Circuit Type E (P3)
Figure 1-9. Pin Circuit Type F (P0.0, P0.1)
2
PROGRAM MEMORY (ROM)
REGISTER ARCHITECTURE
ADDRESS SPACES S3C84E5/C84E9/P84E9
2-4
Figure 2-2. Internal Register File Organization
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F
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~ ~
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F
REGISTER ADDRESSING
S3C84E5/C84E9/P84E9 ADDRESS SPACES
2-13
Figure 2-9. Register File Addressing
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F
ADDRESS SPACES S3C84E5/C84E9/P84E9
2-16
Figure 2-11. 4-Bit Working Register Addressing
Figure 2-12. 4-Bit Working Register Addressing Example
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ADDRESS SPACES S3C84E5/C84E9/P84E9
2-18
Figure 2-14. 8-Bit Working Register Addressing Example
SYSTEM AND USER STACK
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3
ADDRESSING MODES S3C84E5/C84E9/P84E9
3-2
REGISTER ADDRESSING MODE (R)
Figure 3-1. Register Addressing
Figure 3-2. Working Register Addressing
INDIRECT REGISTER ADDRESSING MODE (IR)
ADDRESSING MODES S3C84E5/C84E9/P84E9
3-4
Figure 3-4. Indirect Register Addressing to Program Memory
~ ~ ~ ~
Figure 3-5. Indirect Working Register Addressing to Register File
ADDRESSING MODES S3C84E5/C84E9/P84E9
3-6
Figure 3-6. Indirect Working Register Addressing to Program or Data Memory
INDEXED ADDRESSING MODE (X)
~ ~ ~ ~
+
ADDRESSING MODES S3C84E5/C84E9/P84E9
+
3-8
INDEXED ADDRESSING MODE (Continued)
~ ~
Figure 3-8. Indexed Addressing to Program or Data Memory with Short Offset
+
~ ~
Figure 3-9. Indexed Addressing to Program or Data Memory
DIRECT ADDRESS MODE (DA)
DIRECT ADDRESS MODE (Continued)
INDIRECT ADDRESS MODE (IA)
RELATIVE ADDRESS MODE (RA)
+
IMMEDIATE MODE (IM)
4
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FLAGS -
System Flags Register
D5H
Set 1
Figure 4-1. Register Description Format
ADCON
BTCON
CLKCON
FLAGS
IMR
IPH
IPL
IPR
IRQ
OSCCON
P0CONH
P0CONL
P1CONH
P1CONL
P2CONH
P2CONL
P2INT
P2INTPND
P3CONH
P3CONL
P4CONH
P4CONL
P4INT
P4INTPND
PP
RP0
RP1
SPH
SPL
STPCON Stop Control Register E5H Set 1, Bank 0
SYM
T1CON0
T1CON1
TACON
TBCON
TINTPND
UARTCON
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UARTPND
WTCON
5
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INTERRUPT STRUCTURE S3C84E5/C84E9/P84E9
5-4
Figure 5-2. S3C84E5/C84E9/P84E9 Interrupt Structure
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Figure 5-8. Interrupt Priority Register (IPR)
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6
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ADC
ADD
AND
BAND
BCP
BITC
BITR
BITS
BOR
BTJRF
BTJRT
BXOR
CALL
CCF
CLR
COM
CP
CPIJE
CPIJNE
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DA
DEC
DECW
DI
DIV
DJNZ
EI
ENTER
EXIT
IDLE
INC
INCW
IRET
JP
JR
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LD
LDB
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LDC/LDE
LDCD/LDED
LDCI/LDEI
LDCPD/LDEPD
LDCPI/LDEPI
LDW
MULT
NEXT
NOP
OR
POP
POPUD
POPUI
PUSH
PUSHUD Push User Stack (Decrementing)
PUSHUI
RCF
RET
RL
RLC
RR
RRC
SB0
SB1
SBC
SCF
SRA
SRP/SRP0/SRP1
STOP
SUB
SWAP
TCM
TM
WFI
XOR
7
CLOCK CIRCUIT S3C84E5/C84E9/P84E9
7-2
Figure 7-3. System Clock Circuit Diagram
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Figure 7-5. Oscillator Control Register (OSCCON)
STOP Control Register (STPCON)
Figure 7-6. STOP Control Register (STPCON)
8
SYSTEM RESET
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POWER-DOWN MODES
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9
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I/O PORTS S3C84E5/C84E9/P84E9
9-4
Figure 9-2. Port 0 Low Byte Control Register (P0CONL)
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I/O PORTS S3C84E5/C84E9/P84E9
9-6
Figure 9-4. Port 1 Low-Byte Control Register (P1CONL)
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Figure 9-5. Port 2 High-Byte Control Register (P2CONH)
Figure 9-6. Port 2 Low-Byte Control Register (P2CONL)
Figure 9-7. Port 2 Interrupt Pending Register (P2INTPND)
Figure 9-8. Port 2 Interrupt Control Register (P2INT)
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Figure 9-10. Port 3 Low-Byte Control Register (P3CONL)
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Figure 9-11. Port 4 High-Byte Control Register (P4CONH)
Figure 9-12. Port 4 Low-Byte Control Register (P4CONL)
Figure 9-13. Port 4 Interrupt Pending Register (P4INTPND)
Figure 9-14. Port 4 Interrupt Control Register (P4INT)
10
BASIC TIMER S3C84E5/C84E9/P84E9
10-2
Figure 10-1. Basic Timer Control Register (BTCON)
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11
8-BIT TIMER A
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BLOCK DIAGRAM
Figure 11-2. Timer A Functional Block Diagram
8-BIT TIMER B
TIMER B CONTROL REGISTER (TBCON)
Figure 11-4. Timer B Control Register (TBCON)
Figure 11-5. Timer B Data Registers (TBDATAH, TBDATAL)
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Figure 11-6. Timer B Output Flip Flop Waveforms in Repeat Mode
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F
12
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Figure 12-1. Timer 1(0,1) Control Register (T1CON0, T1CON1)
Figure 12-2. Timer A, Timer 1(0,1) Pending Register (TINTPND)
16-BIT TIMER 1(0,1) S3C84E5/C84E9/P84E9
12-6
BLOCK DIAGRAM
Figure 12-3. Timer 1(0,1) Functional Block Diagram
F
13
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Figure 13-1. UART Control Register (UARTCON)
Not used (must keep always 0)
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UART S3C84E5/C84E9/P84E9
13-8
BLOCK DIAGRAM
Figure 13-5. UART Functional Block Diagram
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UART S3C84E5/C84E9/P84E9
13-12
Figure 13-8. Timing Diagram for UART Mode 2 Operation
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14
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WATCH TIMER CIRCUIT DIAGRAM
Figure 14-1. Watch Timer Circuit Diagram
F
15
OVERVIEW
FUNCTION DESCRIPTION
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S3C84E5/C84E9/P84E9 A/D CONVERTER
15-3
Figure 15-2. A/D Converter Data Register (ADDATAH, ADDATAL)
Figure 15-3. A/D Converter Circuit Diagram
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F
16
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17
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ELECTRICAL DATA S3C84E5/C84E9/P84E9
17-8
A
Figure 17-4. Stop Mode Release Timing Initiated by RESET
Figure 17-5. Stop Mode (Main) Release Timing Initiated by Interrupts
Figure 17-6. Stop Mode (Sub) Release Timing Initiated by Interrupts
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18
The S3C84E5/C84E9/P84E9 microcontrollers are available in a 42-SDIP-600, 44-QFP-1010 package.
42-SDIP-600
Figure 18-1. 42-SDIP-600 Package Dimensions
MECHANICAL DATA S3C84E5/C84E9/P84E9
44-QFP-1010
18-2
Figure 18-2. 44-QFP-1010 Package Dimensions
19
S3P84E9
(42-SDIP)
Figure 19-1. S3P84E9 Pin Assignments (42-SDIP Package)
OTP VERSION S3C84E5/C84E9/P84E9
19-2
S3P84E9
(44-QFP)
Figure 19-2. S3P84E9 Pin Assignments (44-QFP Package)
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20
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S3C84E5/C84E9/P84E9 DEVELOPMENT TOOLS
20-3
TB84E5/84E9
Figure 20-2. S3C84E5/S3C84E9/S3P84E9 Target Board Configuration
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Table 20-3. The Port 0.0 and Port 0.1 selection setting Sub-OSC Setting Description
44-PIN DIP SOCKET
Figure 20-3. 44-Pin Connector Pin Assignment for TB84E5/84E9
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S3C8- SERIES MASK ROM ORDER FORM
@ : Assembly site code, Y : Last number of assembly year, WW : Week of assembly
@ YWW Device Name
SEC Device Name
@ YWW @ YWW
S3C8- SERIES REQUEST FOR PRODUCTION AT CUSTOMER RISK
S3C84E5/C84E9 MASK OPTION SELECTION FORM
F