Page
Features
Low Voltage Reset
Built-in Reset circuit LVR
Errata VER
BGR
Reset
VDD
D.C. Electrical Characteristics
Parameter Symbol Conditions Min Typ Max Unit
VDD = 4.5V to RUN mode MHz CPU clock VDD = Vlvr to 5.5
Pull-up resistor
A.C. Electrical Characteristics
Main Oscillator Frequency
Main Oscillator Clock Stabilization TimePAGE
Sub Oscillator Frequency
Data Retention Supply Voltage in Stop Mode
10. Uart Timing Characteristics in Mode 0
Parameter Symbol Min Typ Max Unit
Oscillator Test Condition Min Typ Max Unit
11. A/D Converter Electrical Characteristics
12. LVR Low Voltage Reset Circuit Characteristics
Comparison of S3P84E9 and S3C84E5/C84E9 Features
Operating Voltage RangePAGE
S3C84E5/C84E9/P84E9
Important Notice
Iii
Part Programming Model
Uart
Table of Contents
Chapter Interrupt Structure
Overview
Part II Hardware Descriptions
Vii
Chapter
Viii
HEX2ROM
List of Figures
Title Number
10-2
10-4
11-8
Xii
12-4
12-5
13-3
13-7
17-2
17-11
Xvi
Chapter Bit Timer A/B
Chapter Bit Timer 10,1
Chapter Watch Timer
Chapter Converter Configuring A/D Converter 15-6
Register Full Register Name Identifier Number
Instruction Full Register Name Mnemonic Number
LDC/LDE
LDCD/LDED
LDCI/LDEI
LDCPD/LDEPD
S3C84E5/C84E9/P84E9 Microcontroller
Product Overview
S3C8-SERIES Microcontrollers
Features
CPU
Block Diagram
S3C84E5/C84E9/P84E9 Block Diagram
NRESET
PIN Assignment
Top View
44-QFP
S3C84E5
S3C84E9
S3P84E9
Sdip
S3C84E5/C84E9/P84E9 Pin Descriptions Circuit Share
Type Description Number Pins
PIN Descriptions
INT0-INT10
AVREF, Avss
BUZ
Test
Pin Circuit Type B nRESET
PIN Circuits
Pin Circuit Type D P0.2-P0.7, P1, P4.3-P4.5
Pin Circuit Type E P3
Address Spaces
Overview
0FFH
Program Memory ROM
HEX
Register Architecture
S3C84E5/C84E9/P84E9 Register Type Summary Number of Bytes
Total Addressable Bytes
590
Set1 Bank
Page01 PagePage00 Set
Register page Pointer PP
MSB LSB
SRP
RAMCL0 CLR
Djnz R0,RAMCL0 CLR
RAMCL1 CLR
Register SET
Prime Register Space
FFH F0H E0H D0H C0H
Set Bank
C0H BFH
F7H
Working Registers
F8H
Using the Register Pointers
Programming TIP Setting the Register Pointers
SRP1
SRP0
#80H RP0 ← 80H
R0,R1 ← R0 + R1
R0,R2
+ R2 + C
Register Addressing
Bit Register Pair
FFH E0H D0H C0H BFH
Control Registers System
Register Pointers
Prime Registers
Common Working Register Area C0H-CFH
RP1 → C8H-CFH
FFH F0H
E0H D0H C0H BFH
Programming TIP Addressing the Common Working Register Area
Examples
Example
BIT Working Register Addressing
RP0 RP1
R6 Opcode
13 -Bit Working Register Addressing
14 -Bit Working Register Addressing Example
System and User Stack
Stack Operations
Stack Pointers SPL, SPH
High Address
SPL,#0FFH SPL ← FFH
Push RP0
Push RP1
POP RP1
Addressing Modes
Register Addressing Mode R
Opcode
DEC Cntr
Operand
@SHIFT
Indirect Register Addressing Mode IR
Address
Call @RR2 JP @RR2
Indirect Register Addressing Mode
Register Pair
Indirect Working Register Addressing to Register File
LCD
LDE
Indexed Addressing Mode
Index
LDC
Indexed Addressing Mode
Offset
Indexed Addressing to Program or Data Memory
Direct Address Mode DA
10. Direct Addressing for Load Instructions
Call Display
Direct Address Mode
JOB1
Indirect Address Mode IA
Call #40H
Relative Address Mode RA
ULT,$+OFFSET
LD R0,#0AAH
Immediate Mode IM
Operand Opcode
Control Registers
Set 1 Registers Register Name Mnemonic Decimal Hex
Set 1, Bank 0 Registers Register Name Mnemonic Decimal Hex
Set 1, Bank 1 Registers Register Name Mnemonic Decimal Hex
Bit Identifier Reset Value Read/Write Bit Addressing
Mode Carry Flag C
Zero Flag Z
Sign Flag S
Adcon A/D Converter Control Register F7H Set 1, Bank
Btcon Basic Timer Control Register
D3H
Clkcon System Clock Control Register
D4H
CPU Clock System Clock Selection Bits note
Fxx/2
Flags System Flags Register
D5H
IMR Interrupt Mask Register
DDH
IPH Instruction Pointer High Byte
DAH
IPL Instruction Pointer Low Byte
DBH
IPR Interrupt Priority Register
FFH
IRQ Interrupt Request Register
DCH
Osccon Oscillator Control Register FBH Set 1, Bank
Sub-system Oscillator Driving Ability Control Bit
Main System Oscillator Control Bit
Sub System Oscillator Control Bit
P0.7/TACAP Configuration Bits
P0.6/TACK Configuration Bits
P0.5/T1CAP0 Configuration Bits
P0.4/T1OUT1 Configuration Bits
P0.3/T1CK1 Configuration Bits
P0.2/T1CAP1 Configuration Bits
P0.1/XTout Configuration Bits
P0.0/XTin Configuration Bits
P1CONH Port 1 Control Register High Byte E8H Set 1, Bank
P1.5/TXD Configuration Bits
P1.4/RXD Configuration Bits
P1.3/BZOUT Configuration Bits
P1.2/T1OUT0 Configuration Bits
P1.1/T1CK0 Configuration Bits
P1.0/TAOUT Configuration Bits
P2CONH Port 2 Control Register High Byte EAH Set 1, Bank
P2.7/INT7
P2.6/ INT6
P2.5/ INT5
P2CONL Port 2 Control Register Low Byte EBH Set 1, Bank
P2.3/INT3
P2.2/INT2
P2.1/INT1
P2INT Port 2 Interrupt Control Register
ECH
P2INTPND Port 2 Interrupt Pending Register
EDH
P3CONH Port 3 Control Register High Byte EEH Set 1, Bank
P3.7/ADC7
4P3.6/ADC6
2P3.5/ADC5
P3CONL Port 3 Control Register Low Byte EFH Set 1, Bank
P3.3/ADC3
4P3.2/ADC2
3P3.1/ADC1
Input mode Push-pull output mode
P4CONH Port 4 Control Register High Byte F0H Set 1, Bank
P4.5
P4.4
P4CONL Port 4 Control Register Low Byte F1H Set 1, Bank
P4.3/TBPWM
P4.2/INT10
P4.1/INT9
P4.2 External Interrupt INT10 Enable Bit
P4.1 External Interrupt INT9 Enable Bit
P4.0 External Interrupt INT8 Enable Bit
P4INT Port 4 Interrupt Control Register
P4INTPND Port 4 Interrupt Pending Register
F3H
P4.2/PND10 Interrupt Pending Bit
P4.1/PND9 Interrupt Pending Bit
PP Register Page Pointer
DFH
Destination Register Page Selection Bits
Source Register Page Selection Bits
RP0 Register Pointer
D6H
RP1 Register Pointer
D7H
SPH Stack Pointer High Byte
D8H
Set
SPL Stack Pointer Low Byte
Stpcon Stop Control Register E5H Set 1, Bank
Stop Control Bits
SYM System Mode Register
Fast Interrupt Enable Bit
Global Interrupt Enable Bit note
DEH
T1CON0 Timer 10 Control Register E8H Set 1, Bank
T1CON1 Timer 11 Control Register E9H Set 1, Bank
Tacon Timer a Control Register E1H Set 1, Bank
Tbcon Timer B Control Register
D0H
Tintpnd Timer A, Timer 1 Interrupt Pending Register E0H
Multiprocessor Communication 1 Enable Bit for mode 2 only
Serial Data Receive Enable Bit
Receive Interrupt Enable Bit
Transmit Interrupt Enable Bit
Control Register
Uartpnd Uart Pending and parity control F4H Set 1, Bank
Wtcon Watch Timer Control Register FAH Set 1, Bank
Interrupt Structure
Levels
Vectors
Sources
Interrupt Types
Levels Type 1 IRQn Type 2 IRQn Type 3 IRQn Vectors Sources
S3C84E5/C84E9/P84E9 Interrupt Structure
Vectors Sources ResetClear
Levels
HEX 7FFFH 3FFFH
Interrupt Vector Addresses
Interrupt Vector Area
Level
Interrupt Control Register Overview Function Description
ENABLE/DISABLE Interrupt Instructions EI, DI
SYSTEM-LEVEL Interrupt Control Registers
Interrupt Function Diagram
Interrupt Processing Control Points
Peripheral Interrupt Control Registers
IRQ1 IRQ2 IRQ3 IRQ4 IRQ5 IRQ6 IRQ7
System Mode Register SYM
IRQ0
LSB IRQ1 IRQ0 IRQ7 IRQ6 IRQ5 IRQ4 IRQ3 IRQ2
Interrupt Mask Register IMR
MSB
Interrupt Priority Register IPR
Group a
IRQ0, IRQ1
Group B IRQ2, IRQ3, IRQ4 Group C IRQ5, IRQ6, IRQ7
Interrupt Priority Register IPR
Interrupt Request Register IRQ
Interrupt Request Register IRQ
Pending Bits Cleared by the Service Routine
Interrupt Pending Function Types
Overview
Pending Bits Cleared Automatically by Hardware
Interrupt Service Routines
Interrupt Source Polling Sequence
Generating Interrupt Vector Addresses
Nesting of Vectored Interrupts
Instruction SET
Data Types
Register Addressing
Addressing Modes
LDE
LDC
Lded
Ldcd
Logic Instructions
Bit Manipulation Instructions
CPU Control Instructions
Flags Register Flags
System Flags Register Flags
Flag Descriptions
Instruction Set Symbols
Symbol Description
Instruction SET Notation
Flag Notation Conventions
IML
Immediate long addressing mode #data Data =
IRR
Opcode Quick Reference
Opcode MAP Lower Nibble HEX
Djnz INC Next
R1,R2 R2,R1
Djnz INC NOP
Idle
Condition Codes
Condition Codes Binary Mnemonic Description Flags Set
Instruction Descriptions
ADC Add with Carry
ADC
ADD Add
ADD
Format
Bytes Cycles Opcode
Logical
Band Bit
Src Opc
Given R1 = 07H and register 01H = 05H
R1,01H.1 R1 = 06H, register 01H = 05H
BCP Bit Compare
BCP
Hex Dst
Bitc Bit Complement
Bitc
Bitr Bit Reset
BITRdst.b Operation dstb ←
Bits Bit Set
BITSdst.b Operation dstb ←
BOR Bit or
BOR
PC jumps to Skip location
Btjrf Bit Test, Jump Relative on False
Btjrf SKIP,R1.3
Btjrt Bit Test, Jump Relative on True
Btjrt
If srcb is a 1, then PC ← PC + dst
Btjrt SKIP,R1.1
Bxor Bit XOR
R1,01H.1 R1 = 06H, register 01H 03H
Call Call Procedure
Call dst Operation SP ← SP-1
@SP ← PCL
@SP ← PCH
CCF Complement Carry Flag
CCF
Operation C ← not C
Format Bytes Cycles Opcode Hex
00H Register 00H
CLR Clear
CLRdst Operation dst ←
COM Complement
COMdst Operation dst ← not dst
Opc Dst Examples Given R1 = 07H and register 07H = 0F1H
0F8H
Format Bytes Cycles Opcode Addr Mode Hex Dst Src
CP Compare
Operation dst-src
UGE,SKIP INC Skip
Cpije Compare, Increment, and Jump on Equal
Cpije
Dst,src,RA
If dst-src = 0, PC
Cpijne Compare, Increment, and Jump on Non-Equal
Cpijne
Opc Src Dst
Example Given R1 = 02H, R2 = 03H, and register 03H = 04H
DA Decimal Adjust
DAdst Operation dst ← DA dst
After DA
ADD ADC
3CH
Contents of the destination operand are decremented by one
DEC Decrement
DECdst Operation dst ← dst-1
Opc Dst Examples Given R1 = 03H and register 03H = 10H
Decw Decrement Word
Decw
Decw RR0
Loop Decw RR0
DI Disable Interrupts
Operation SYM 0 ←
DIV Divide Unsigned
Operation dst ÷ src
Set if the divisor or the quotient = 0 cleared otherwise
Set if MSB of the quotient = 1 cleared otherwise
SRP #0C0H Djnz R1,LOOP
Djnz Decrement and Jump if Non-Zero
DJNZr,dst Operation r ¬ r
EI Enable Interrupts
SYM 0 ←
EI instruction is executed
No flags are affected
Enter Enter
Enter
Operation IP ← @SP
Exit Exit
Exit
Idle Idle Operation
Idle
INC Increment
INCdst Operation dst ← dst +
INC 00H
0DH INC @R0
Incw Increment Word
Incw dst Operation dst ← dst +
0FFH Incw RR0
Loop Incw RR0
Iret Interrupt Return
Iret
Flags ← @SP PC ↔ IP
Flags ← Flags
JP Jump
Labelw
JR C,LABELX
JR Jump Relative
Hex Dst CcB Cc = 0 to F
Opc Dst Src = 0 to F
LD Load
Dst ← src
0AH
LD R0,#LOOPR1
= 0FFH, R1 = 0AH
LD #LOOPR0,R1
LDB Load Bit
LDB
Dst Examples Given R0 = 06H and general register 00H = 05H
R0,00H.2 07H, register 00H 05H
Bytes Cycles Opcode Addr Mode Hex Dst Src
LDC/LDE Load Memory
LDC
LDE
LDC/LDE
R0,1104H ← contents of program memory location 1104H = 88H
R0,1104H ← contents of external data memory location = 98H
Operation dst ← src
LDCD/LDED Load Memory and Decrement
Ldcd dst,src Lded dst,src
LDCI/LDEI Load Memory and Increment
Ldci
Ldei
Rr ← rr +
LDCPD/LDEPD Load Memory with Pre-Decrement
Ldcpd dst,src Ldepd dst,src
Operation rr ← rr
Irr Examples Given R0 = 77H, R6 = 30H, and R7 = 00H
LDCPI/LDEPI Load Memory with Pre-Increment
Ldcpi dst,src Ldepi dst,src
Operation rr ← rr +
Irr Examples Given R0 = 7FH, R6 = 21H, and R7 = 0FFH
LDW Load Word
LDW RR6,RR4
0FH
0EDH
Mult Multiply Unsigned
Mult dst,src
Operation dst ← dst × src
00H, @01H Register 00H 00H, register 01H 0C0H
Operation PC ← @IP
Next Next
Next
NOP No Operation
NOP
00H,#02H Register 00H
Or Logical or
0BFH
POP Pop from Stack
POPdst Operation dst ← @SP
Hex Dst Examples
0FBH
6FH
Popud Pop User Stack Decrementing
Popud dst,src
Example Given Register 00H = 01H and register 01H = 70H
Popui Pop User Stack Incrementing
Popui dst,src
0FFH = 0AAH, SPH = 0FFH, SPL = 0FFH
Push Push to Stack
Push src Operation SP ← SP
Pushud Push User Stack Decrementing
Pushud
IR ← IR
Decremented stack pointer
Pushui @00H,01H
Pushui Push User Stack Incrementing
Pushui dst,src Operation IR ← IR +
Flags Cleared to
RCF Reset Carry Flag
RCF
RET Return
RET
Operation PC ← @SP
Example Given SP
RL Rotate Left
RLdst Operation C ← dst
00H Register 00H 54H, C =
RLC Rotate Left through Carry
RLCdst Operation dst 0 ← C
RR Rotate Right
RRdst Operation C ← dst
00H Register 00H 2AH, C =
RRC Rotate Right through Carry
RRCdst Operation dst 7 ← C
Operation Bank ←
SB0 Select Bank
SB0
SB1 Select Bank
SB1
SBC Subtract with Carry
0AH SBC
Opc 4DF Example The statement SCF sets the carry flag to
SCF Set Carry Flag
SCF
00H Register 00H 0CD, C =
SRA Shift Right Arithmetic
SRAdst
SRP/SRP0/SRP1 Set Register Pointer
SRP
SRP0
SRP1
Stop Stop Operation
Stop
SUB Subtract
Swap Swap Nibbles
Swap dst
Opc Dst Examples Given Register 00H
Swap 00H Swap @02H
TCM Test Complement under Mask
R0,R1 = 0C7H, R1 = 02H, Z =
R0,@R1 = 0C7H, R1 = 02H, register 02H = 23H, Z =
00H,01H Register 00H 2BH, register 01H 02H, Z =
Operation dst and src
TM Test under Mask
TMdst,src
Enable global interrupt
WFI Wate for Interrupt
WFI
Opc 4n3F
XOR Logical Exclusive or
R0,R1 = 0C5H, R1 = 02H
R0,@R1 = 0E4H, R1 = 02H, register 02H = 23H
00H,01H Register 00H 29H, register 01H 02H
Clock Circuit
System Clock Circuit
Crystal or Ceramic Oscillator Crystal Oscillator
S3C84E5 S3C84E9 S3P84E9
Clock Status During POWER-DOWN Modes
System Clock Circuit Diagram
System Clock Control Register Clkcon
S3C84E5/C84E9/P84E9 REV.0
Oscillator Control Register Osccon
System Reset
Normal Mode Reset Operation
S3C84E5/C84E9/P84E9 Reset and POWER-DOWN
Overview
Reset and POWER-DOWN S3C84E5/C84E9/P84E9
Hardware Reset Values
Dec Hex Timer B control register
Converter data registerlow byte
S3C84E5/C84E9/P84E9RESET and POWER-DOWN
Converter data registerhigh byte
Timer A, 1 interrupt pending register
Reset and POWER-DOWNS3C84E5/C84E9/P84E9
Uart baud rate data register high
Uart baud rate data register low
POWER-DOWN Modes
Stop Mode
Using Reset to Release Stop Mode
Using an External Interrupt to Release Stop Mode
How to Enter into Stop Mode
Idle Mode
O Ports
S3C84E5/C84E9/P84E9 Port Configuration Overview
Port Configuration Options
Port Data Registers
Port
Port 0 Control Register P0CONH/P0CONL
P0.3/T1CK1 Configuration Bits
P0.2/T1CAP1 Configuration Bits
P0.1/XTout Configuration Bits
P0.0/XTin Configuration Bits
Port 1 Control Register P1CONH, P1CONL
P1.5/TXD Configuration Bits
P1.4/RXD Configuration Bits
P1.3/BZOUT Configuration Bits
P1.2/T1OUT0 Configuration Bits
P1.1/T1CK0 Configuration Bits
P1.0/TAOUT Configuration Bits
Port 2 Control Register P2CONH, P2CONL
P2.7/INT7 Configuration Bits
P2.6/INT6 Configuration Bits
P2.5/INT5 Configuration Bits
P2.4/INT4 Configuration Bits
P2.3/INT3 Configuration Bits
P2.2/INT2 Configuration Bits
P2.1/INT1 Configuration Bits
P2.0/INT0 Configuration Bits
P2.7/PND7, Interrupt Pending Bit
P2.6/PND6, Interrupt Pending Bit
P2.5/PND5, Interrupt Pending Bit
P2.4/PND4, Interrupt Pending Bit
P2.7 External Interrupt INT7 Enable Bit
P2.6 External Interrupt INT6 Enable Bit
P2.5 External Interrupt INT5 Enable Bit
P2.4 External Interrupt INT4 Enable Bit
P3.7/ADC7 Configuration Bits
P3.6/ADC6 Configuration Bits
P3.5/ADC5 Configuration Bits
P3.4/ADC4 Configuration Bits
P3.3/ADC3 Configuration Bits
P3.2/ADC2 Configuration Bits
P3.1/ADC1 Configuration Bits
P3.0/ADC0 Configuration Bits
Port 4 Control Register P4CONH, P4CONL
P4.5 Configuration Bits
P4.4 Configuration Bits
P4.3/TBPWM Configuration Bits
P4.2/INT10 Configuration Bits
P4.2 External Interrupt INT10 Enable Bit
P4.1 External Interrupt INT9 Enable Bit
P4.0 External Interrupt INT8 Enable Bit
P4.2/PND10, Interrupt Pending Bit
Basic Timer
Basic Timer BT
Basic Timer Control Register Btcon
10-1
Basic Timer Control Register Btcon
10-2
Basic Timer Function Description
Watchdog Timer Function
Oscillation Stabilization Interval Timer Function
10-3
DIV
MUX
OVF
10-4
11-1
11 8-BIT Timer A/B
BIT Timer a
Timer a Interrupts IRQ1, Vectors C0H and C2H
Interval Timer Function
Pulse Width Modulation Mode
Capture Mode
Timer a Control Register Tacon
11-3
Block Diagram
11-4
BIT Timer B
11-5
Timer B Control Register Tbcon
11-6
Timer B Pulse Width Calculations
11-7
11-8
Tbdatal = DFH Tbdatah = 1FH
Tbdatal = 7FH Tbdatah = 7FH
0100H Reset address
ORG
Start DI
P4CONLH,#03H
Programming TIP To generate a one pulse signal through P4.3
TBDATAH,# Set 40 μs
TBDATAL,#
Set any value except 00H
Programming TIP Using the Timer a
Programming TIP Using the Timer B
0BEh,TBUNINT
Main Main Routine JRT,MAIN Tbunint
11-12
S3C84E5/C84E9/P84E9 BIT Timer 10,1
12-1
Timer 10,1 Interrupts IRQ2, Vectors C4H, C6H, C8H and CAH
Interval Mode match
BIT Timer 10,1 S3C84E5/C84E9/P84E9
12-2
12-3
PWM Mode
Timer 10,1 Control Register T1CON0, T1CON1
Timer 10,1 Control Register T1CON0, T1CON1
12-4
Timer A, Timer 10,1 Pending Register Tintpnd
12-5
12-6
Programming TIP Using the Timer
0C4h,TIM1INT
T1DATAH0,#00F0h T1DATAH0=00h, T1DATAL0=F0h
SB0 Main Main Routine JRT,MIAN TIM1INT
13-1
Programming Procedure
Uart
Uart Control Register Uartcon
13-2
13-3
MSB MS1 MS0 MCE RE TB8 RB8 RIE TIE LSB
MS1 MS0
Uart Interrupt Pending Register Uartpnd
Must keep always
Always
MSB PEN RPE RIP TIP LSB
Uart Data Register Udata
13-5
13-6
Uart Baud Rate Data Register BRDATAH, Brdatal
Baud Rate Calculations
Brdatah Brdatal
Decimal Hex
13-8
Tx Control
Rx Control
Uart Mode 0 Function Description
Mode 0 Transmit Procedure
Mode 0 Receive Procedure
13-9
Uart Mode 1 Function Description
Mode 1 Transmit Procedure
Mode 1 Receive Procedure
13-10
Uart Mode 2 Function Description
Parity disable mode PEN =
Parity enable mode PEN =
Mode 2 Transmit Procedure
Timing Diagram for Uart Mode 2 Operation
13-12
13-13
Serial Communication for Multiprocessor Configurations
Sample Protocol for Master/Slave Interaction
13-14
Setup Procedure for Multiprocessor Communications
Full-Duplex Multi-S3C84E5/C84E9/P84E9 Interconnect
Watch Timer
14-1
Reset
WTCON.7
WTCON.6
WTCON.1
Watch Timer Circuit Diagram
14-3
Programming TIP Using the Watch Timer
0CCh,WTINT
Main Main Routine JRT,MIAN Wtint
WTCON,#11111110b Pending clear
15-1
15 A/D Converter
Function Description
Converter Control Register Adcon
15-2
15-3
Internal Reference Voltage Levels
Conversion Timing
EOC Addata
15-4
15-5
Internal A/D Conversion Procedure
S3C84E5
Programming TIP Configuring A/D Converter
LOW Voltage Reset
16-1
16-2
Electrical Data
17-1
Input/Output Capacitance
Parameter Symbol Conditions Rating Unit
Absolute Maximum Ratings
D.C. Electrical Characteristics
VDD = Vlvr
17-4
VDD = 4.5 V to RUN mode MHz CPU clock VDD = Vlvr to 5.5
VDD = 4.5 V to 5.5 100 TA = 25C Stop mode VDD = Vlvr to 3.3
A.C. Electrical Characteristics
Ports NRESET input
Interrupt input
VDD = 5 180 High, low width
When released by a reset 216/f
Wait time TWAIT when released by an interrupt
Main Oscillator Frequency fOSC1
Main Oscillator Clock Stabilization Time tST1
17-7
Subsystem Oscillator crystal Stabilization Time tST2
Xtin
Data Retention Supply Voltage in Stop Mode
Stop mode Supply voltage Data retention
Data retention
Stop mode, Vdddr = 2.0 Supply current
Stop Mode Sub Release Timing Initiated by Interrupts
17-9
10. Uart Timing Characteristics in Mode 0 10 MHz
11. A/D Converter Electrical Characteristics
Parameter Symbol Test Conditions Min Typ Max Unit
12. LVR Low Voltage Reset Circuit Characteristics
17-12
Mechanical Data
MAX
MIN
18-1
QFP-1010
18-2
19-1
19 S3P84E9 OTP Version
Sdip
44-QFP
SDAT/TBPWM/P4.3 SCLK/INT10/P4.2
VPP/TEST
19-2
Test MEM
Operating Mode Characteristics
REG
19-4
Development Tools
Shine
Sasm
Sama Assembler
Target Boards
OTP
OTP Programming Socket Adapter
Emulator SMDS2+ or SK-1000
TB84E5/84E9 Target Board
20-3
Power Selection Settings for TB84E5/84E9
To UserVcc Settings Operating Mode Comments
Idle LED
Stop LED
PIN DIP Socket
TB84E5/84E9 Adapter Cable for 44pin Connector Package
20-6
S3C8- Series Mask ROM Order Form
SEC
S3C8- Series Request for Production AT Customer Risk
Risk Order Information
Customer Risk Order Agreement
Order Quantity and Delivery Schedule
S3C84E5/C84E9 Mask Option Selection Form
Attachment Check one
Prom
Customer Checksum Company Name Signature Engineer