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Samsung S3C84E5 user manual WFI Wate for Interrupt, Wfi, Opc 4n3F, Enable global interrupt

Models: S3C84E5

1 316

Page 213

INSTRUCTION SET	S3C84E5/C84E9/P84E9

WFI — Wate for Interrupt

WFI

Operation: The CPU is effectively halted before an interrupt occurs, except that DMA transfers can still take place during this wait state. The WFI status can be released by an internal interrupt, including a fast interrupt.

Flags: No flags are affected.

Format:

Bytes Cycles Opcode (Hex)

opc

1 4n3F

(n = 1, 2, 3, … )

Example: The following sample program structure shows the sequence of operations that follow a "WFI" statement:

Main program

EI	(Enable global interrupt)
WFI	(Wait for interrupt)
(Next instruction)
.
.
.
Interrupt occurs
Interrupt service routine
.
.
.
Clear interrupt flag
IRET

Service routine completed

6-86

Page 213

Image 213

Samsung S3C84E5 user manual WFI Wate for Interrupt, Wfi, Opc 4n3F, Enable global interrupt, Wait for interrupt

Contents

Page Low Voltage Reset FeaturesBuilt-in Reset circuit LVR Errata VERReset VDDBGR Parameter Symbol Conditions Min Typ Max Unit D.C. Electrical CharacteristicsPull-up resistor VDD = 4.5V to RUN mode MHz CPU clock VDD = Vlvr to 5.5Main Oscillator Frequency A.C. Electrical CharacteristicsMain Oscillator Clock Stabilization TimePAGE Sub Oscillator Frequency10. Uart Timing Characteristics in Mode 0 Data Retention Supply Voltage in Stop ModeParameter Symbol Min Typ Max Unit Oscillator Test Condition Min Typ Max Unit12. LVR Low Voltage Reset Circuit Characteristics 11. A/D Converter Electrical CharacteristicsComparison of S3P84E9 and S3C84E5/C84E9 Features Operating Voltage RangePAGES3C84E5/C84E9/P84E9 Important Notice Part Programming Model UartIii Table of Contents Overview Chapter Interrupt StructureVii Part II Hardware DescriptionsViii ChapterHEX2ROM Title Number List of Figures10-4 10-211-8 Xii12-5 12-413-3 13-717-11 17-2Xvi Chapter Bit Timer 10,1 Chapter Bit Timer A/BChapter Watch Timer Chapter Converter Configuring A/D Converter 15-6Register Full Register Name Identifier Number Instruction Full Register Name Mnemonic Number LDCD/LDED LDC/LDELDCI/LDEI LDCPD/LDEPDProduct Overview S3C8-SERIES MicrocontrollersS3C84E5/C84E9/P84E9 Microcontroller CPU FeaturesS3C84E5/C84E9/P84E9 Block Diagram Block DiagramPIN Assignment NRESETTop View 44-QFPS3C84E9 S3C84E5S3P84E9 SdipType Description Number Pins PIN DescriptionsS3C84E5/C84E9/P84E9 Pin Descriptions Circuit Share AVREF, Avss INT0-INT10BUZ TestPIN Circuits Pin Circuit Type B nRESETPin Circuit Type D P0.2-P0.7, P1, P4.3-P4.5 Pin Circuit Type E P3 Overview Address SpacesProgram Memory ROM HEX0FFH S3C84E5/C84E9/P84E9 Register Type Summary Number of Bytes Register ArchitectureTotal Addressable Bytes 590Page01 PagePage00 Set Set1 BankMSB LSB Register page Pointer PPRAMCL0 CLR SRPDjnz R0,RAMCL0 CLR RAMCL1 CLRRegister SET FFH F0H E0H D0H C0H Prime Register SpaceSet Bank C0H BFHWorking Registers F8HF7H Programming TIP Setting the Register Pointers Using the Register PointersSRP1 SRP0R0,R1 ← R0 + R1 #80H RP0 ← 80HR0,R2 + R2 + CBit Register Pair Register AddressingControl Registers System FFH E0H D0H C0H BFHRegister Pointers Prime RegistersRP1 → C8H-CFH Common Working Register Area C0H-CFHFFH F0H E0H D0H C0H BFHExamples Programming TIP Addressing the Common Working Register AreaExample BIT Working Register AddressingR6 Opcode RP0 RP113 -Bit Working Register Addressing 14 -Bit Working Register Addressing Example Stack Operations System and User StackStack Pointers SPL, SPH High AddressPush RP0 SPL,#0FFH SPL ← FFHPush RP1 POP RP1Addressing Modes Opcode Register Addressing Mode RDEC Cntr OperandIndirect Register Addressing Mode IR Address@SHIFT Indirect Register Addressing Mode Register PairCall @RR2 JP @RR2 Indirect Working Register Addressing to Register File LDE LCDIndex Indexed Addressing ModeIndexed Addressing Mode OffsetLDC Indexed Addressing to Program or Data Memory 10. Direct Addressing for Load Instructions Direct Address Mode DADirect Address Mode JOB1Call Display Call #40H Indirect Address Mode IAULT,$+OFFSET Relative Address Mode RAImmediate Mode IM Operand OpcodeLD R0,#0AAH Set 1 Registers Register Name Mnemonic Decimal Hex Control RegistersSet 1, Bank 0 Registers Register Name Mnemonic Decimal Hex Set 1, Bank 1 Registers Register Name Mnemonic Decimal Hex Mode Carry Flag C Bit Identifier Reset Value Read/Write Bit AddressingZero Flag Z Sign Flag SAdcon A/D Converter Control Register F7H Set 1, Bank D3H Btcon Basic Timer Control RegisterD4H Clkcon System Clock Control RegisterCPU Clock System Clock Selection Bits note Fxx/2D5H Flags System Flags RegisterDDH IMR Interrupt Mask RegisterDAH IPH Instruction Pointer High ByteIPL Instruction Pointer Low Byte DBHFFH IPR Interrupt Priority RegisterDCH IRQ Interrupt Request RegisterSub-system Oscillator Driving Ability Control Bit Osccon Oscillator Control Register FBH Set 1, BankMain System Oscillator Control Bit Sub System Oscillator Control BitP0.6/TACK Configuration Bits P0.7/TACAP Configuration BitsP0.5/T1CAP0 Configuration Bits P0.4/T1OUT1 Configuration BitsP0.2/T1CAP1 Configuration Bits P0.3/T1CK1 Configuration BitsP0.1/XTout Configuration Bits P0.0/XTin Configuration BitsP1.5/TXD Configuration Bits P1.4/RXD Configuration BitsP1CONH Port 1 Control Register High Byte E8H Set 1, Bank P1.2/T1OUT0 Configuration Bits P1.3/BZOUT Configuration BitsP1.1/T1CK0 Configuration Bits P1.0/TAOUT Configuration BitsP2.7/INT7 P2CONH Port 2 Control Register High Byte EAH Set 1, BankP2.6/ INT6 P2.5/ INT5P2.3/INT3 P2CONL Port 2 Control Register Low Byte EBH Set 1, BankP2.2/INT2 P2.1/INT1ECH P2INT Port 2 Interrupt Control RegisterEDH P2INTPND Port 2 Interrupt Pending RegisterP3.7/ADC7 P3CONH Port 3 Control Register High Byte EEH Set 1, Bank4P3.6/ADC6 2P3.5/ADC5P3.3/ADC3 P3CONL Port 3 Control Register Low Byte EFH Set 1, Bank4P3.2/ADC2 3P3.1/ADC1P4CONH Port 4 Control Register High Byte F0H Set 1, Bank Input mode Push-pull output modeP4.5 P4.4P4.3/TBPWM P4CONL Port 4 Control Register Low Byte F1H Set 1, BankP4.2/INT10 P4.1/INT9P4.1 External Interrupt INT9 Enable Bit P4.2 External Interrupt INT10 Enable BitP4.0 External Interrupt INT8 Enable Bit P4INT Port 4 Interrupt Control RegisterF3H P4INTPND Port 4 Interrupt Pending RegisterP4.2/PND10 Interrupt Pending Bit P4.1/PND9 Interrupt Pending BitDFH PP Register Page PointerDestination Register Page Selection Bits Source Register Page Selection BitsD6H RP0 Register PointerRP1 Register Pointer D7HD8H SPH Stack Pointer High ByteSet SPL Stack Pointer Low ByteStop Control Bits Stpcon Stop Control Register E5H Set 1, BankFast Interrupt Enable Bit SYM System Mode RegisterGlobal Interrupt Enable Bit note DEHT1CON0 Timer 10 Control Register E8H Set 1, Bank T1CON1 Timer 11 Control Register E9H Set 1, Bank Tacon Timer a Control Register E1H Set 1, Bank D0H Tbcon Timer B Control RegisterTintpnd Timer A, Timer 1 Interrupt Pending Register E0H Serial Data Receive Enable Bit Multiprocessor Communication 1 Enable Bit for mode 2 onlyReceive Interrupt Enable Bit Transmit Interrupt Enable BitControl Register Uartpnd Uart Pending and parity control F4H Set 1, Bank Wtcon Watch Timer Control Register FAH Set 1, Bank Levels Interrupt StructureVectors SourcesLevels Type 1 IRQn Type 2 IRQn Type 3 IRQn Vectors Sources Interrupt TypesS3C84E5/C84E9/P84E9 Interrupt Structure Levels Vectors Sources ResetClearInterrupt Vector Addresses Interrupt Vector AreaHEX 7FFFH 3FFFH Level ENABLE/DISABLE Interrupt Instructions EI, DI SYSTEM-LEVEL Interrupt Control RegistersInterrupt Control Register Overview Function Description Interrupt Processing Control Points Interrupt Function DiagramPeripheral Interrupt Control Registers System Mode Register SYM IRQ0IRQ1 IRQ2 IRQ3 IRQ4 IRQ5 IRQ6 IRQ7 Interrupt Mask Register IMR MSBLSB IRQ1 IRQ0 IRQ7 IRQ6 IRQ5 IRQ4 IRQ3 IRQ2 Group a Interrupt Priority Register IPRIRQ0, IRQ1 Group B IRQ2, IRQ3, IRQ4 Group C IRQ5, IRQ6, IRQ7Interrupt Priority Register IPR Interrupt Request Register IRQ Interrupt Request Register IRQInterrupt Pending Function Types Pending Bits Cleared by the Service RoutineOverview Pending Bits Cleared Automatically by HardwareInterrupt Source Polling Sequence Interrupt Service RoutinesNesting of Vectored Interrupts Generating Interrupt Vector AddressesData Types Instruction SETRegister Addressing Addressing ModesLDC LDELded LdcdLogic Instructions Bit Manipulation Instructions CPU Control Instructions System Flags Register Flags Flags Register FlagsFlag Descriptions Symbol Description Instruction Set SymbolsInstruction SET Notation Flag Notation ConventionsImmediate long addressing mode #data Data = IRRIML Opcode MAP Lower Nibble HEX Opcode Quick ReferenceR1,R2 R2,R1 Djnz INC NextDjnz INC NOP IdleCondition Codes Binary Mnemonic Description Flags Set Condition CodesInstruction Descriptions ADC ADC Add with CarryADD ADD AddFormat Bytes Cycles OpcodeLogical Src Opc Band BitGiven R1 = 07H and register 01H = 05H R1,01H.1 R1 = 06H, register 01H = 05HBCP BCP Bit CompareBitc Bit Complement BitcHex Dst BITRdst.b Operation dstb ← Bitr Bit ResetBITSdst.b Operation dstb ← Bits Bit SetBOR BOR Bit orBtjrf Bit Test, Jump Relative on False Btjrf SKIP,R1.3PC jumps to Skip location Btjrt Btjrt Bit Test, Jump Relative on TrueIf srcb is a 1, then PC ← PC + dst Btjrt SKIP,R1.1R1,01H.1 R1 = 06H, register 01H 03H Bxor Bit XORCall dst Operation SP ← SP-1 Call Call Procedure@SP ← PCL @SP ← PCHCCF CCF Complement Carry FlagOperation C ← not C Format Bytes Cycles Opcode HexCLR Clear CLRdst Operation dst ←00H Register 00H COMdst Operation dst ← not dst COM ComplementOpc Dst Examples Given R1 = 07H and register 07H = 0F1H 0F8HCP Compare Format Bytes Cycles Opcode Addr Mode Hex Dst SrcOperation dst-src UGE,SKIP INC SkipCpije Cpije Compare, Increment, and Jump on EqualDst,src,RA If dst-src = 0, PCCpijne Cpijne Compare, Increment, and Jump on Non-EqualOpc Src Dst Example Given R1 = 02H, R2 = 03H, and register 03H = 04HDAdst Operation dst ← DA dst DA Decimal AdjustAfter DA ADD ADC3CH DEC Decrement Contents of the destination operand are decremented by oneDECdst Operation dst ← dst-1 Opc Dst Examples Given R1 = 03H and register 03H = 10HDecw Decw Decrement WordDecw RR0 Loop Decw RR0Operation SYM 0 ← DI Disable InterruptsOperation dst ÷ src DIV Divide UnsignedSet if the divisor or the quotient = 0 cleared otherwise Set if MSB of the quotient = 1 cleared otherwiseDjnz Decrement and Jump if Non-Zero DJNZr,dst Operation r ¬ rSRP #0C0H Djnz R1,LOOP SYM 0 ← EI Enable InterruptsEI instruction is executed No flags are affectedEnter Enter EnterExit Exit ExitOperation IP ← @SP Idle Idle Idle OperationINCdst Operation dst ← dst + INC IncrementINC 00H 0DH INC @R0Incw dst Operation dst ← dst + Incw Increment Word0FFH Incw RR0 Loop Incw RR0Iret Iret Interrupt ReturnFlags ← @SP PC ↔ IP Flags ← FlagsLabelw JP JumpJR Jump Relative Hex Dst CcB Cc = 0 to FJR C,LABELX LD Load Dst ← srcOpc Dst Src = 0 to F LD R0,#LOOPR1 0AH= 0FFH, R1 = 0AH LD #LOOPR0,R1LDB LDB Load BitDst Examples Given R0 = 06H and general register 00H = 05H R0,00H.2 07H, register 00H 05HLDC/LDE Load Memory Bytes Cycles Opcode Addr Mode Hex Dst SrcLDC LDER0,1104H ← contents of program memory location 1104H = 88H R0,1104H ← contents of external data memory location = 98HLDC/LDE LDCD/LDED Load Memory and Decrement Ldcd dst,src Lded dst,srcOperation dst ← src Ldci LDCI/LDEI Load Memory and IncrementLdei Rr ← rr +Ldcpd dst,src Ldepd dst,src LDCPD/LDEPD Load Memory with Pre-DecrementOperation rr ← rr Irr Examples Given R0 = 77H, R6 = 30H, and R7 = 00HLdcpi dst,src Ldepi dst,src LDCPI/LDEPI Load Memory with Pre-IncrementOperation rr ← rr + Irr Examples Given R0 = 7FH, R6 = 21H, and R7 = 0FFHLDW RR6,RR4 LDW Load Word0FH 0EDHMult dst,src Mult Multiply UnsignedOperation dst ← dst × src 00H, @01H Register 00H 00H, register 01H 0C0HNext Next NextOperation PC ← @IP NOP NOP No OperationOr Logical or 0BFH00H,#02H Register 00H POPdst Operation dst ← @SP POP Pop from StackHex Dst Examples 0FBHPopud Pop User Stack Decrementing Popud dst,src6FH Popui Pop User Stack Incrementing Popui dst,srcExample Given Register 00H = 01H and register 01H = 70H Push Push to Stack Push src Operation SP ← SP0FFH = 0AAH, SPH = 0FFH, SPL = 0FFH Pushud Pushud Push User Stack DecrementingIR ← IR Decremented stack pointerPushui Push User Stack Incrementing Pushui dst,src Operation IR ← IR +Pushui @00H,01H RCF Reset Carry Flag RCFFlags Cleared to RET RET ReturnOperation PC ← @SP Example Given SPRLdst Operation C ← dst RL Rotate LeftRLC Rotate Left through Carry RLCdst Operation dst 0 ← C00H Register 00H 54H, C = RRdst Operation C ← dst RR Rotate RightRRC Rotate Right through Carry RRCdst Operation dst 7 ← C00H Register 00H 2AH, C = SB0 Select Bank SB0Operation Bank ← SB1 SB1 Select Bank0AH SBC SBC Subtract with CarrySCF Set Carry Flag SCFOpc 4DF Example The statement SCF sets the carry flag to SRA Shift Right Arithmetic SRAdst00H Register 00H 0CD, C = SRP SRP/SRP0/SRP1 Set Register PointerSRP0 SRP1Stop Stop Stop OperationSUB Subtract Swap dst Swap Swap NibblesOpc Dst Examples Given Register 00H Swap 00H Swap @02HR0,R1 = 0C7H, R1 = 02H, Z = TCM Test Complement under MaskR0,@R1 = 0C7H, R1 = 02H, register 02H = 23H, Z = 00H,01H Register 00H 2BH, register 01H 02H, Z =TM Test under Mask TMdst,srcOperation dst and src WFI Wate for Interrupt Enable global interruptWFI Opc 4n3FR0,R1 = 0C5H, R1 = 02H XOR Logical Exclusive orR0,@R1 = 0E4H, R1 = 02H, register 02H = 23H 00H,01H Register 00H 29H, register 01H 02HSystem Clock Circuit Clock CircuitCrystal or Ceramic Oscillator Crystal Oscillator S3C84E5 S3C84E9 S3P84E9System Clock Circuit Diagram Clock Status During POWER-DOWN ModesS3C84E5/C84E9/P84E9 REV.0 System Clock Control Register ClkconOscillator Control Register Osccon Normal Mode Reset Operation System ResetS3C84E5/C84E9/P84E9 Reset and POWER-DOWN OverviewHardware Reset Values Dec Hex Timer B control registerReset and POWER-DOWN S3C84E5/C84E9/P84E9 S3C84E5/C84E9/P84E9RESET and POWER-DOWN Converter data registerhigh byteConverter data registerlow byte Reset and POWER-DOWNS3C84E5/C84E9/P84E9 Timer A, 1 interrupt pending registerUart baud rate data register high Uart baud rate data register lowStop Mode POWER-DOWN ModesUsing Reset to Release Stop Mode Using an External Interrupt to Release Stop ModeIdle Mode How to Enter into Stop ModeS3C84E5/C84E9/P84E9 Port Configuration Overview Port Configuration OptionsO Ports Port Data Registers Port 0 Control Register P0CONH/P0CONL PortP0.2/T1CAP1 Configuration Bits P0.3/T1CK1 Configuration BitsP0.1/XTout Configuration Bits P0.0/XTin Configuration BitsP1.5/TXD Configuration Bits P1.4/RXD Configuration BitsPort 1 Control Register P1CONH, P1CONL P1.2/T1OUT0 Configuration Bits P1.3/BZOUT Configuration BitsP1.1/T1CK0 Configuration Bits P1.0/TAOUT Configuration BitsPort 2 Control Register P2CONH, P2CONL P2.6/INT6 Configuration Bits P2.7/INT7 Configuration BitsP2.5/INT5 Configuration Bits P2.4/INT4 Configuration BitsP2.2/INT2 Configuration Bits P2.3/INT3 Configuration BitsP2.1/INT1 Configuration Bits P2.0/INT0 Configuration BitsP2.6/PND6, Interrupt Pending Bit P2.7/PND7, Interrupt Pending BitP2.5/PND5, Interrupt Pending Bit P2.4/PND4, Interrupt Pending BitP2.6 External Interrupt INT6 Enable Bit P2.7 External Interrupt INT7 Enable BitP2.5 External Interrupt INT5 Enable Bit P2.4 External Interrupt INT4 Enable BitP3.6/ADC6 Configuration Bits P3.7/ADC7 Configuration BitsP3.5/ADC5 Configuration Bits P3.4/ADC4 Configuration BitsP3.2/ADC2 Configuration Bits P3.3/ADC3 Configuration BitsP3.1/ADC1 Configuration Bits P3.0/ADC0 Configuration BitsPort 4 Control Register P4CONH, P4CONL P4.4 Configuration Bits P4.5 Configuration BitsP4.3/TBPWM Configuration Bits P4.2/INT10 Configuration BitsP4.1 External Interrupt INT9 Enable Bit P4.2 External Interrupt INT10 Enable BitP4.0 External Interrupt INT8 Enable Bit P4.2/PND10, Interrupt Pending BitBasic Timer BT Basic TimerBasic Timer Control Register Btcon 10-110-2 Basic Timer Control Register BtconWatchdog Timer Function Basic Timer Function DescriptionOscillation Stabilization Interval Timer Function 10-3MUX DIVOVF 10-411 8-BIT Timer A/B BIT Timer a11-1 Interval Timer Function Timer a Interrupts IRQ1, Vectors C0H and C2HPulse Width Modulation Mode Capture Mode11-3 Timer a Control Register Tacon11-4 Block Diagram11-5 BIT Timer B11-6 Timer B Control Register Tbcon11-7 Timer B Pulse Width CalculationsTbdatal = DFH Tbdatah = 1FH Tbdatal = 7FH Tbdatah = 7FH11-8 ORG 0100H Reset addressStart DI P4CONLH,#03HTBDATAH,# Set 40 μs Programming TIP To generate a one pulse signal through P4.3TBDATAL,# Set any value except 00HProgramming TIP Using the Timer a 0BEh,TBUNINT Programming TIP Using the Timer BMain Main Routine JRT,MAIN Tbunint 11-1212-1 S3C84E5/C84E9/P84E9 BIT Timer 10,1Interval Mode match Timer 10,1 Interrupts IRQ2, Vectors C4H, C6H, C8H and CAHBIT Timer 10,1 S3C84E5/C84E9/P84E9 12-2PWM Mode Timer 10,1 Control Register T1CON0, T1CON112-3 12-4 Timer 10,1 Control Register T1CON0, T1CON112-5 Timer A, Timer 10,1 Pending Register Tintpnd12-6 0C4h,TIM1INT Programming TIP Using the TimerT1DATAH0,#00F0h T1DATAH0=00h, T1DATAL0=F0h SB0 Main Main Routine JRT,MIAN TIM1INTProgramming Procedure Uart13-1 13-2 Uart Control Register UartconMSB MS1 MS0 MCE RE TB8 RB8 RIE TIE LSB MS1 MS013-3 Must keep always Uart Interrupt Pending Register UartpndAlways MSB PEN RPE RIP TIP LSB13-5 Uart Data Register UdataUart Baud Rate Data Register BRDATAH, Brdatal Baud Rate Calculations13-6 Decimal Hex Brdatah BrdatalTx Control Rx Control13-8 Mode 0 Transmit Procedure Uart Mode 0 Function DescriptionMode 0 Receive Procedure 13-9Mode 1 Transmit Procedure Uart Mode 1 Function DescriptionMode 1 Receive Procedure 13-10Parity disable mode PEN = Uart Mode 2 Function DescriptionParity enable mode PEN = Mode 2 Transmit Procedure13-12 Timing Diagram for Uart Mode 2 OperationSerial Communication for Multiprocessor Configurations Sample Protocol for Master/Slave Interaction13-13 Setup Procedure for Multiprocessor Communications Full-Duplex Multi-S3C84E5/C84E9/P84E9 Interconnect13-14 14-1 Watch TimerWTCON.7 ResetWTCON.6 WTCON.114-3 Watch Timer Circuit Diagram0CCh,WTINT Programming TIP Using the Watch TimerMain Main Routine JRT,MIAN Wtint WTCON,#11111110b Pending clear15 A/D Converter Function Description15-1 15-2 Converter Control Register Adcon15-3 Conversion Timing Internal Reference Voltage LevelsEOC Addata 15-4Internal A/D Conversion Procedure S3C84E515-5 Programming TIP Configuring A/D Converter 16-1 LOW Voltage Reset16-2 17-1 Electrical DataParameter Symbol Conditions Rating Unit Absolute Maximum RatingsInput/Output Capacitance VDD = Vlvr D.C. Electrical CharacteristicsVDD = 4.5 V to RUN mode MHz CPU clock VDD = Vlvr to 5.5 VDD = 4.5 V to 5.5 100 TA = 25C Stop mode VDD = Vlvr to 3.317-4 Ports NRESET input A.C. Electrical CharacteristicsInterrupt input VDD = 5 180 High, low widthWait time TWAIT when released by an interrupt When released by a reset 216/fMain Oscillator Frequency fOSC1 Main Oscillator Clock Stabilization Time tST1Subsystem Oscillator crystal Stabilization Time tST2 Xtin17-7 Stop mode Supply voltage Data retention Data Retention Supply Voltage in Stop ModeData retention Stop mode, Vdddr = 2.0 Supply current17-9 Stop Mode Sub Release Timing Initiated by Interrupts10. Uart Timing Characteristics in Mode 0 10 MHz Parameter Symbol Test Conditions Min Typ Max Unit 11. A/D Converter Electrical Characteristics17-12 12. LVR Low Voltage Reset Circuit CharacteristicsMAX Mechanical DataMIN 18-118-2 QFP-101019 S3P84E9 OTP Version Sdip19-1 SDAT/TBPWM/P4.3 SCLK/INT10/P4.2 44-QFPVPP/TEST 19-2Operating Mode Characteristics REGTest MEM 19-4 Shine Development ToolsSasm Sama AssemblerOTP Target BoardsOTP Programming Socket Adapter Emulator SMDS2+ or SK-100020-3 TB84E5/84E9 Target BoardTo UserVcc Settings Operating Mode Comments Power Selection Settings for TB84E5/84E9Idle LED Stop LEDPIN DIP Socket 20-6 TB84E5/84E9 Adapter Cable for 44pin Connector PackageSEC S3C8- Series Mask ROM Order FormRisk Order Information S3C8- Series Request for Production AT Customer RiskCustomer Risk Order Agreement Order Quantity and Delivery ScheduleAttachment Check one S3C84E5/C84E9 Mask Option Selection FormProm Customer Checksum Company Name Signature Engineer

WFI — Wate for Interrupt

WFI

Format:

opc

1 4n3F

(Enable global interrupt)

WFI

(Wait for interrupt)