Samsung S3C84E5 user manual Indexed Addressing Mode

S3C84E5/C84E9/P84E9 ADDRESSING MODES

INDEXED ADDRESSING MODE (X)

Indexed (X) addressing mode adds an offset value to a base address during instruction execution in order to calculate the effective operand address (see Figure 3-7). You can use Indexed addressing mode to access locations in the internal register file or in external memory. Please note, however, that you cannot access locations C0H–FFH in set 1 using indexed addressing mode.

In short offset Indexed addressing mode, the 8-bit displacement is treated as a signed integer in the range –128 to +127. This applies to external memory accesses only (see Figure 3-8.)

For register file addressing, an 8-bit base address provided by the instruction is added to an 8-bit offset contained in a working register. For external memory accesses, the base address is stored in the working register pair designated in the instruction. The 8-bit or 16-bit offset given in the instruction is then added to that base address (see Figure 3-9).

The only instruction that supports indexed addressing mode for the internal register file is the Load instruction (LD). The LDC and LDE instructions support indexed addressing mode for internal program memory and for external data memory, when implemented.

Two-Operand

Instruction

Example

Program Memory

Base Address

dst/src x

OPCODE

							Register File
							RP0 or RP1
		Value used in				~	~
					Instruction
							OPERAND
	+
						~	~
			3 LSBs
	INDEX
Point to One of the
Woking Register
				(1 of 8)

Selected RP points to start of working register block

Sample Instruction:

LD R0, #BASE[R1] ; Where BASE is an 8-bit immediate value

Figure 3-7. Indexed Addressing to Register File

3-7