Samsung S3C84E5 Interrupt Mask Register IMR, Msb, LSB IRQ1 IRQ0 IRQ7 IRQ6 IRQ5 IRQ4 IRQ3 IRQ2

S3C84E5/C84E9/P84E9 INTERRUPT STRUCTURE

INTERRUPT MASK REGISTER (IMR)

The interrupt mask register, IMR (set 1, DDH) is used to enable or disable interrupt processing for individual interrupt levels. After a reset, all IMR bit values are undetermined and must therefore be written to their required settings by the initialization routine.

Each IMR bit corresponds to a specific interrupt level: bit 1 to IRQ1, bit 2 to IRQ2, and so on. When the IMR bit of an interrupt level is cleared to "0", interrupt processing for that level is disabled (masked). When you set a level's IMR bit to "1", interrupt processing for the level is enabled (not masked).

The IMR register is mapped to register location DDH in set 1. Bit values can be read and written by instructions using the Register addressing mode.

MSB

Interrupt Mask Register (IMR)

DDH ,Set 1, R/W

.7 .6 .5 .4 .3 .2 .1 .0

LSB

IRQ1 IRQ0

IRQ7 IRQ6 IRQ5 IRQ4 IRQ3 IRQ2

Interrupt level # enable bit

0 = Disable IRQ# interrupt

1 = Enable IRQ# interrupt

Figure 5-6. Interrupt Mask Register (IMR)

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