12-6

16-BIT TIMER 1(0,1)	S3C84E5/C84E9/P84E9

BLOCK DIAGRAM

	T1CON.7-.5
					T1CON.0	T1OVF
						T1OVF
	f xx/1024		Data Bus	Overflow	Pending
	f xx/1024		Data Bus		Pending
	f xx/256				TINTPND
	f xx/64		8		TINTPND
	f xx/8	M	8
	f xx/8
	fxx/1
	fxx/1	U		Clear
		U	16-bit Up-Counter			T1CON.2
		X

			(Read Only)
T1CK			(Read Only)
T1CK
	V S					T1CON.1
	S			Match		T1CON.1
			16-bit Comparator	Match	M	T1INT
			16-bit Comparator		M
	M				U	Pending
	M				X	TINTPND
T1CAP	U					TINTPND
T1CAP	U
	X		16-bit Timer Buffer			T1OUT(T1PWM)
						T1OUT(T1PWM)
						M
						U
						X
T1CON.4-.3
			16-bit Timer Data Register		T1CON.4.3
			(T1DATAH/L)		T1CON.4.3

Data Bus

NOTES:

1.When PWM mode, match signal cannot clear counter.

2.Pending bit is located at TINTPND register.

Figure 12-3. Timer 1(0,1) Functional Block Diagram

Page 262

Image 262

Contents

Page Built-in Reset circuit LVR FeaturesLow Voltage Reset Errata VER VDD ResetBGR D.C. Electrical Characteristics Parameter Symbol Conditions Min Typ Max Unit VDD = 4.5V to RUN mode MHz CPU clock VDD = Vlvr to 5.5 Pull-up resistor Main Oscillator Clock Stabilization TimePAGE A.C. Electrical CharacteristicsMain Oscillator Frequency Sub Oscillator Frequency Parameter Symbol Min Typ Max Unit Data Retention Supply Voltage in Stop Mode10. Uart Timing Characteristics in Mode 0 Oscillator Test Condition Min Typ Max Unit Comparison of S3P84E9 and S3C84E5/C84E9 Features 11. A/D Converter Electrical Characteristics12. LVR Low Voltage Reset Circuit Characteristics Operating Voltage RangePAGE S3C84E5/C84E9/P84E9 Important Notice Uart Part Programming ModelIii Table of Contents Chapter Interrupt Structure Overview Part II Hardware Descriptions Vii Chapter Viii HEX2ROM List of Figures Title Number 11-8 10-210-4 Xii 13-3 12-412-5 13-7 17-2 17-11 Xvi Chapter Watch Timer Chapter Bit Timer A/BChapter Bit Timer 10,1 Chapter Converter Configuring A/D Converter 15-6 Register Full Register Name Identifier Number Instruction Full Register Name Mnemonic Number LDCI/LDEI LDC/LDELDCD/LDED LDCPD/LDEPD S3C8-SERIES Microcontrollers Product OverviewS3C84E5/C84E9/P84E9 Microcontroller Features CPU Block Diagram S3C84E5/C84E9/P84E9 Block Diagram Top View NRESETPIN Assignment 44-QFP S3P84E9 S3C84E5S3C84E9 Sdip PIN Descriptions Type Description Number PinsS3C84E5/C84E9/P84E9 Pin Descriptions Circuit Share BUZ INT0-INT10AVREF, Avss Test Pin Circuit Type B nRESET PIN Circuits Pin Circuit Type D P0.2-P0.7, P1, P4.3-P4.5 Pin Circuit Type E P3 Address Spaces Overview HEX Program Memory ROM0FFH Total Addressable Bytes Register ArchitectureS3C84E5/C84E9/P84E9 Register Type Summary Number of Bytes 590 Set1 Bank Page01 PagePage00 Set Register page Pointer PP MSB LSB Djnz R0,RAMCL0 CLR SRPRAMCL0 CLR RAMCL1 CLR Register SET Set Bank Prime Register SpaceFFH F0H E0H D0H C0H C0H BFH F8H Working RegistersF7H SRP1 Using the Register PointersProgramming TIP Setting the Register Pointers SRP0 R0,R2 #80H RP0 ← 80HR0,R1 ← R0 + R1 + R2 + C Register Addressing Bit Register Pair Register Pointers FFH E0H D0H C0H BFHControl Registers System Prime Registers FFH F0H Common Working Register Area C0H-CFHRP1 → C8H-CFH E0H D0H C0H BFH Example Programming TIP Addressing the Common Working Register AreaExamples BIT Working Register Addressing RP0 RP1 R6 Opcode 13 -Bit Working Register Addressing 14 -Bit Working Register Addressing Example Stack Pointers SPL, SPH System and User StackStack Operations High Address Push RP1 SPL,#0FFH SPL ← FFHPush RP0 POP RP1 Addressing Modes DEC Cntr Register Addressing Mode ROpcode Operand Address Indirect Register Addressing Mode IR@SHIFT Register Pair Indirect Register Addressing ModeCall @RR2 JP @RR2 Indirect Working Register Addressing to Register File LCD LDE Indexed Addressing Mode Index Offset Indexed Addressing ModeLDC Indexed Addressing to Program or Data Memory Direct Address Mode DA 10. Direct Addressing for Load Instructions JOB1 Direct Address ModeCall Display Indirect Address Mode IA Call #40H Relative Address Mode RA ULT,$+OFFSET Operand Opcode Immediate Mode IMLD R0,#0AAH Control Registers Set 1 Registers Register Name Mnemonic Decimal Hex Set 1, Bank 0 Registers Register Name Mnemonic Decimal Hex Set 1, Bank 1 Registers Register Name Mnemonic Decimal Hex Zero Flag Z Bit Identifier Reset Value Read/Write Bit AddressingMode Carry Flag C Sign Flag S Adcon A/D Converter Control Register F7H Set 1, Bank Btcon Basic Timer Control Register D3H CPU Clock System Clock Selection Bits note Clkcon System Clock Control RegisterD4H Fxx/2 Flags System Flags Register D5H IMR Interrupt Mask Register DDH IPL Instruction Pointer Low Byte IPH Instruction Pointer High ByteDAH DBH IPR Interrupt Priority Register FFH IRQ Interrupt Request Register DCH Main System Oscillator Control Bit Osccon Oscillator Control Register FBH Set 1, BankSub-system Oscillator Driving Ability Control Bit Sub System Oscillator Control Bit P0.5/T1CAP0 Configuration Bits P0.7/TACAP Configuration BitsP0.6/TACK Configuration Bits P0.4/T1OUT1 Configuration Bits P0.1/XTout Configuration Bits P0.3/T1CK1 Configuration BitsP0.2/T1CAP1 Configuration Bits P0.0/XTin Configuration Bits P1.4/RXD Configuration Bits P1.5/TXD Configuration BitsP1CONH Port 1 Control Register High Byte E8H Set 1, Bank P1.1/T1CK0 Configuration Bits P1.3/BZOUT Configuration BitsP1.2/T1OUT0 Configuration Bits P1.0/TAOUT Configuration Bits P2.6/ INT6 P2CONH Port 2 Control Register High Byte EAH Set 1, BankP2.7/INT7 P2.5/ INT5 P2.2/INT2 P2CONL Port 2 Control Register Low Byte EBH Set 1, BankP2.3/INT3 P2.1/INT1 P2INT Port 2 Interrupt Control Register ECH P2INTPND Port 2 Interrupt Pending Register EDH 4P3.6/ADC6 P3CONH Port 3 Control Register High Byte EEH Set 1, BankP3.7/ADC7 2P3.5/ADC5 4P3.2/ADC2 P3CONL Port 3 Control Register Low Byte EFH Set 1, BankP3.3/ADC3 3P3.1/ADC1 P4.5 Input mode Push-pull output modeP4CONH Port 4 Control Register High Byte F0H Set 1, Bank P4.4 P4.2/INT10 P4CONL Port 4 Control Register Low Byte F1H Set 1, BankP4.3/TBPWM P4.1/INT9 P4.0 External Interrupt INT8 Enable Bit P4.2 External Interrupt INT10 Enable BitP4.1 External Interrupt INT9 Enable Bit P4INT Port 4 Interrupt Control Register P4.2/PND10 Interrupt Pending Bit P4INTPND Port 4 Interrupt Pending RegisterF3H P4.1/PND9 Interrupt Pending Bit Destination Register Page Selection Bits PP Register Page PointerDFH Source Register Page Selection Bits RP1 Register Pointer RP0 Register PointerD6H D7H Set SPH Stack Pointer High ByteD8H SPL Stack Pointer Low Byte Stpcon Stop Control Register E5H Set 1, Bank Stop Control Bits Global Interrupt Enable Bit note SYM System Mode RegisterFast Interrupt Enable Bit DEH T1CON0 Timer 10 Control Register E8H Set 1, Bank T1CON1 Timer 11 Control Register E9H Set 1, Bank Tacon Timer a Control Register E1H Set 1, Bank Tbcon Timer B Control Register D0H Tintpnd Timer A, Timer 1 Interrupt Pending Register E0H Receive Interrupt Enable Bit Multiprocessor Communication 1 Enable Bit for mode 2 onlySerial Data Receive Enable Bit Transmit Interrupt Enable Bit Control Register Uartpnd Uart Pending and parity control F4H Set 1, Bank Wtcon Watch Timer Control Register FAH Set 1, Bank Vectors Interrupt StructureLevels Sources Interrupt Types Levels Type 1 IRQn Type 2 IRQn Type 3 IRQn Vectors Sources S3C84E5/C84E9/P84E9 Interrupt Structure Vectors Sources ResetClear Levels Interrupt Vector Area Interrupt Vector AddressesHEX 7FFFH 3FFFH Level SYSTEM-LEVEL Interrupt Control Registers ENABLE/DISABLE Interrupt Instructions EI, DIInterrupt Control Register Overview Function Description Interrupt Function Diagram Interrupt Processing Control Points Peripheral Interrupt Control Registers IRQ0 System Mode Register SYMIRQ1 IRQ2 IRQ3 IRQ4 IRQ5 IRQ6 IRQ7 MSB Interrupt Mask Register IMRLSB IRQ1 IRQ0 IRQ7 IRQ6 IRQ5 IRQ4 IRQ3 IRQ2 IRQ0, IRQ1 Interrupt Priority Register IPRGroup a Group B IRQ2, IRQ3, IRQ4 Group C IRQ5, IRQ6, IRQ7 Interrupt Priority Register IPR Interrupt Request Register IRQ Interrupt Request Register IRQ Overview Pending Bits Cleared by the Service RoutineInterrupt Pending Function Types Pending Bits Cleared Automatically by Hardware Interrupt Service Routines Interrupt Source Polling Sequence Generating Interrupt Vector Addresses Nesting of Vectored Interrupts Register Addressing Instruction SETData Types Addressing Modes Lded LDELDC Ldcd Logic Instructions Bit Manipulation Instructions CPU Control Instructions Flags Register Flags System Flags Register Flags Flag Descriptions Instruction SET Notation Instruction Set SymbolsSymbol Description Flag Notation Conventions IRR Immediate long addressing mode #data Data =IML Opcode Quick Reference Opcode MAP Lower Nibble HEX Djnz INC NOP Djnz INC NextR1,R2 R2,R1 Idle Condition Codes Condition Codes Binary Mnemonic Description Flags Set Instruction Descriptions ADC Add with Carry ADC Format ADD AddADD Bytes Cycles Opcode Logical Given R1 = 07H and register 01H = 05H Band BitSrc Opc R1,01H.1 R1 = 06H, register 01H = 05H BCP Bit Compare BCP Bitc Bitc Bit ComplementHex Dst Bitr Bit Reset BITRdst.b Operation dstb ← Bits Bit Set BITSdst.b Operation dstb ← BOR Bit or BOR Btjrf SKIP,R1.3 Btjrf Bit Test, Jump Relative on FalsePC jumps to Skip location If srcb is a 1, then PC ← PC + dst Btjrt Bit Test, Jump Relative on TrueBtjrt Btjrt SKIP,R1.1 Bxor Bit XOR R1,01H.1 R1 = 06H, register 01H 03H @SP ← PCL Call Call ProcedureCall dst Operation SP ← SP-1 @SP ← PCH Operation C ← not C CCF Complement Carry FlagCCF Format Bytes Cycles Opcode Hex CLRdst Operation dst ← CLR Clear00H Register 00H Opc Dst Examples Given R1 = 07H and register 07H = 0F1H COM ComplementCOMdst Operation dst ← not dst 0F8H Operation dst-src Format Bytes Cycles Opcode Addr Mode Hex Dst SrcCP Compare UGE,SKIP INC Skip Dst,src,RA Cpije Compare, Increment, and Jump on EqualCpije If dst-src = 0, PC Opc Src Dst Cpijne Compare, Increment, and Jump on Non-EqualCpijne Example Given R1 = 02H, R2 = 03H, and register 03H = 04H After DA DA Decimal AdjustDAdst Operation dst ← DA dst ADD ADC 3CH DECdst Operation dst ← dst-1 Contents of the destination operand are decremented by oneDEC Decrement Opc Dst Examples Given R1 = 03H and register 03H = 10H Decw RR0 Decw Decrement WordDecw Loop Decw RR0 DI Disable Interrupts Operation SYM 0 ← Set if the divisor or the quotient = 0 cleared otherwise DIV Divide UnsignedOperation dst ÷ src Set if MSB of the quotient = 1 cleared otherwise DJNZr,dst Operation r ¬ r Djnz Decrement and Jump if Non-ZeroSRP #0C0H Djnz R1,LOOP EI instruction is executed EI Enable InterruptsSYM 0 ← No flags are affected Enter Enter Enter Exit Exit ExitOperation IP ← @SP Idle Idle Operation Idle INC 00H INC IncrementINCdst Operation dst ← dst + 0DH INC @R0 0FFH Incw RR0 Incw Increment WordIncw dst Operation dst ← dst + Loop Incw RR0 Flags ← @SP PC ↔ IP Iret Interrupt ReturnIret Flags ← Flags JP Jump Labelw Hex Dst CcB Cc = 0 to F JR Jump RelativeJR C,LABELX Dst ← src LD LoadOpc Dst Src = 0 to F = 0FFH, R1 = 0AH 0AHLD R0,#LOOPR1 LD #LOOPR0,R1 Dst Examples Given R0 = 06H and general register 00H = 05H LDB Load BitLDB R0,00H.2 07H, register 00H 05H LDC Bytes Cycles Opcode Addr Mode Hex Dst SrcLDC/LDE Load Memory LDE R0,1104H ← contents of external data memory location = 98H R0,1104H ← contents of program memory location 1104H = 88HLDC/LDE Ldcd dst,src Lded dst,src LDCD/LDED Load Memory and DecrementOperation dst ← src Ldei LDCI/LDEI Load Memory and IncrementLdci Rr ← rr + Operation rr ← rr LDCPD/LDEPD Load Memory with Pre-DecrementLdcpd dst,src Ldepd dst,src Irr Examples Given R0 = 77H, R6 = 30H, and R7 = 00H Operation rr ← rr + LDCPI/LDEPI Load Memory with Pre-IncrementLdcpi dst,src Ldepi dst,src Irr Examples Given R0 = 7FH, R6 = 21H, and R7 = 0FFH 0FH LDW Load WordLDW RR6,RR4 0EDH Operation dst ← dst × src Mult Multiply UnsignedMult dst,src 00H, @01H Register 00H 00H, register 01H 0C0H Next Next NextOperation PC ← @IP NOP No Operation NOP 0BFH Or Logical or00H,#02H Register 00H Hex Dst Examples POP Pop from StackPOPdst Operation dst ← @SP 0FBH Popud dst,src Popud Pop User Stack Decrementing6FH Popui dst,src Popui Pop User Stack IncrementingExample Given Register 00H = 01H and register 01H = 70H Push src Operation SP ← SP Push Push to Stack0FFH = 0AAH, SPH = 0FFH, SPL = 0FFH IR ← IR Pushud Push User Stack DecrementingPushud Decremented stack pointer Pushui dst,src Operation IR ← IR + Pushui Push User Stack IncrementingPushui @00H,01H RCF RCF Reset Carry FlagFlags Cleared to Operation PC ← @SP RET ReturnRET Example Given SP RL Rotate Left RLdst Operation C ← dst RLCdst Operation dst 0 ← C RLC Rotate Left through Carry00H Register 00H 54H, C = RR Rotate Right RRdst Operation C ← dst RRCdst Operation dst 7 ← C RRC Rotate Right through Carry00H Register 00H 2AH, C = SB0 SB0 Select BankOperation Bank ← SB1 Select Bank SB1 SBC Subtract with Carry 0AH SBC SCF SCF Set Carry FlagOpc 4DF Example The statement SCF sets the carry flag to SRAdst SRA Shift Right Arithmetic00H Register 00H 0CD, C = SRP0 SRP/SRP0/SRP1 Set Register PointerSRP SRP1 Stop Stop Operation Stop SUB Subtract Opc Dst Examples Given Register 00H Swap Swap NibblesSwap dst Swap 00H Swap @02H R0,@R1 = 0C7H, R1 = 02H, register 02H = 23H, Z = TCM Test Complement under MaskR0,R1 = 0C7H, R1 = 02H, Z = 00H,01H Register 00H 2BH, register 01H 02H, Z = TMdst,src TM Test under MaskOperation dst and src WFI Enable global interruptWFI Wate for Interrupt Opc 4n3F R0,@R1 = 0E4H, R1 = 02H, register 02H = 23H XOR Logical Exclusive orR0,R1 = 0C5H, R1 = 02H 00H,01H Register 00H 29H, register 01H 02H Crystal or Ceramic Oscillator Crystal Oscillator Clock CircuitSystem Clock Circuit S3C84E5 S3C84E9 S3P84E9 Clock Status During POWER-DOWN Modes System Clock Circuit Diagram System Clock Control Register Clkcon S3C84E5/C84E9/P84E9 REV.0 Oscillator Control Register Osccon S3C84E5/C84E9/P84E9 Reset and POWER-DOWN System ResetNormal Mode Reset Operation Overview Dec Hex Timer B control register Hardware Reset ValuesReset and POWER-DOWN S3C84E5/C84E9/P84E9 Converter data registerhigh byte S3C84E5/C84E9/P84E9RESET and POWER-DOWNConverter data registerlow byte Uart baud rate data register high Timer A, 1 interrupt pending registerReset and POWER-DOWNS3C84E5/C84E9/P84E9 Uart baud rate data register low Using Reset to Release Stop Mode POWER-DOWN ModesStop Mode Using an External Interrupt to Release Stop Mode How to Enter into Stop Mode Idle Mode Port Configuration Options S3C84E5/C84E9/P84E9 Port Configuration OverviewO Ports Port Data Registers Port Port 0 Control Register P0CONH/P0CONL P0.1/XTout Configuration Bits P0.3/T1CK1 Configuration BitsP0.2/T1CAP1 Configuration Bits P0.0/XTin Configuration Bits P1.4/RXD Configuration Bits P1.5/TXD Configuration BitsPort 1 Control Register P1CONH, P1CONL P1.1/T1CK0 Configuration Bits P1.3/BZOUT Configuration BitsP1.2/T1OUT0 Configuration Bits P1.0/TAOUT Configuration Bits Port 2 Control Register P2CONH, P2CONL P2.5/INT5 Configuration Bits P2.7/INT7 Configuration BitsP2.6/INT6 Configuration Bits P2.4/INT4 Configuration Bits P2.1/INT1 Configuration Bits P2.3/INT3 Configuration BitsP2.2/INT2 Configuration Bits P2.0/INT0 Configuration Bits P2.5/PND5, Interrupt Pending Bit P2.7/PND7, Interrupt Pending BitP2.6/PND6, Interrupt Pending Bit P2.4/PND4, Interrupt Pending Bit P2.5 External Interrupt INT5 Enable Bit P2.7 External Interrupt INT7 Enable BitP2.6 External Interrupt INT6 Enable Bit P2.4 External Interrupt INT4 Enable Bit P3.5/ADC5 Configuration Bits P3.7/ADC7 Configuration BitsP3.6/ADC6 Configuration Bits P3.4/ADC4 Configuration Bits P3.1/ADC1 Configuration Bits P3.3/ADC3 Configuration BitsP3.2/ADC2 Configuration Bits P3.0/ADC0 Configuration Bits Port 4 Control Register P4CONH, P4CONL P4.3/TBPWM Configuration Bits P4.5 Configuration BitsP4.4 Configuration Bits P4.2/INT10 Configuration Bits P4.0 External Interrupt INT8 Enable Bit P4.2 External Interrupt INT10 Enable BitP4.1 External Interrupt INT9 Enable Bit P4.2/PND10, Interrupt Pending Bit Basic Timer Control Register Btcon Basic TimerBasic Timer BT 10-1 Basic Timer Control Register Btcon 10-2 Oscillation Stabilization Interval Timer Function Basic Timer Function DescriptionWatchdog Timer Function 10-3 OVF DIVMUX 10-4 BIT Timer a 11 8-BIT Timer A/B11-1 Pulse Width Modulation Mode Timer a Interrupts IRQ1, Vectors C0H and C2HInterval Timer Function Capture Mode Timer a Control Register Tacon 11-3 Block Diagram 11-4 BIT Timer B 11-5 Timer B Control Register Tbcon 11-6 Timer B Pulse Width Calculations 11-7 Tbdatal = 7FH Tbdatah = 7FH Tbdatal = DFH Tbdatah = 1FH11-8 Start DI 0100H Reset addressORG P4CONLH,#03H TBDATAL,# Programming TIP To generate a one pulse signal through P4.3TBDATAH,# Set 40 μs Set any value except 00H Programming TIP Using the Timer a Main Main Routine JRT,MAIN Tbunint Programming TIP Using the Timer B0BEh,TBUNINT 11-12 S3C84E5/C84E9/P84E9 BIT Timer 10,1 12-1 BIT Timer 10,1 S3C84E5/C84E9/P84E9 Timer 10,1 Interrupts IRQ2, Vectors C4H, C6H, C8H and CAHInterval Mode match 12-2 Timer 10,1 Control Register T1CON0, T1CON1 PWM Mode12-3 Timer 10,1 Control Register T1CON0, T1CON1 12-4 Timer A, Timer 10,1 Pending Register Tintpnd 12-5 12-6 T1DATAH0,#00F0h T1DATAH0=00h, T1DATAL0=F0h Programming TIP Using the Timer0C4h,TIM1INT SB0 Main Main Routine JRT,MIAN TIM1INT Uart Programming Procedure13-1 Uart Control Register Uartcon 13-2 MS1 MS0 MSB MS1 MS0 MCE RE TB8 RB8 RIE TIE LSB13-3 Always Uart Interrupt Pending Register UartpndMust keep always MSB PEN RPE RIP TIP LSB Uart Data Register Udata 13-5 Baud Rate Calculations Uart Baud Rate Data Register BRDATAH, Brdatal13-6 Brdatah Brdatal Decimal Hex Rx Control Tx Control13-8 Mode 0 Receive Procedure Uart Mode 0 Function DescriptionMode 0 Transmit Procedure 13-9 Mode 1 Receive Procedure Uart Mode 1 Function DescriptionMode 1 Transmit Procedure 13-10 Parity enable mode PEN = Uart Mode 2 Function DescriptionParity disable mode PEN = Mode 2 Transmit Procedure Timing Diagram for Uart Mode 2 Operation 13-12 Sample Protocol for Master/Slave Interaction Serial Communication for Multiprocessor Configurations13-13 Full-Duplex Multi-S3C84E5/C84E9/P84E9 Interconnect Setup Procedure for Multiprocessor Communications13-14 Watch Timer 14-1 WTCON.6 ResetWTCON.7 WTCON.1 Watch Timer Circuit Diagram 14-3 Main Main Routine JRT,MIAN Wtint Programming TIP Using the Watch Timer0CCh,WTINT WTCON,#11111110b Pending clear Function Description 15 A/D Converter15-1 Converter Control Register Adcon 15-2 15-3 EOC Addata Internal Reference Voltage LevelsConversion Timing 15-4 S3C84E5 Internal A/D Conversion Procedure15-5 Programming TIP Configuring A/D Converter LOW Voltage Reset 16-1 16-2 Electrical Data 17-1 Absolute Maximum Ratings Parameter Symbol Conditions Rating UnitInput/Output Capacitance D.C. Electrical Characteristics VDD = Vlvr VDD = 4.5 V to 5.5 100 TA = 25C Stop mode VDD = Vlvr to 3.3 VDD = 4.5 V to RUN mode MHz CPU clock VDD = Vlvr to 5.517-4 Interrupt input A.C. Electrical CharacteristicsPorts NRESET input VDD = 5 180 High, low width Main Oscillator Frequency fOSC1 When released by a reset 216/fWait time TWAIT when released by an interrupt Main Oscillator Clock Stabilization Time tST1 Xtin Subsystem Oscillator crystal Stabilization Time tST217-7 Data retention Data Retention Supply Voltage in Stop ModeStop mode Supply voltage Data retention Stop mode, Vdddr = 2.0 Supply current Stop Mode Sub Release Timing Initiated by Interrupts 17-9 10. Uart Timing Characteristics in Mode 0 10 MHz 11. A/D Converter Electrical Characteristics Parameter Symbol Test Conditions Min Typ Max Unit 12. LVR Low Voltage Reset Circuit Characteristics 17-12 MIN Mechanical DataMAX 18-1 QFP-1010 18-2 Sdip 19 S3P84E9 OTP Version19-1 VPP/TEST 44-QFPSDAT/TBPWM/P4.3 SCLK/INT10/P4.2 19-2 REG Operating Mode CharacteristicsTest MEM 19-4 Sasm Development ToolsShine Sama Assembler OTP Programming Socket Adapter Target BoardsOTP Emulator SMDS2+ or SK-1000 TB84E5/84E9 Target Board 20-3 Idle LED Power Selection Settings for TB84E5/84E9To UserVcc Settings Operating Mode Comments Stop LED PIN DIP Socket TB84E5/84E9 Adapter Cable for 44pin Connector Package 20-6 S3C8- Series Mask ROM Order Form SEC Customer Risk Order Agreement S3C8- Series Request for Production AT Customer RiskRisk Order Information Order Quantity and Delivery Schedule Prom S3C84E5/C84E9 Mask Option Selection FormAttachment Check one Customer Checksum Company Name Signature Engineer

Samsung S3C84E5 user manual 12-6

Models: S3C84E5

16-BIT TIMER 1(0,1)

BLOCK DIAGRAM

(T1DATAH/L)

Figure 12-3. Timer 1(0,1) Functional Block Diagram

12-6