Samsung user manual System Clock Control Register Clkcon, S3C84E5/C84E9/P84E9 REV.0

S3C84E5/C84E9/P84E9 (REV.0) CLOCK CIRCUIT

SYSTEM CLOCK CONTROL REGISTER (CLKCON)

The system clock control register, CLKCON, is located in set 1, address D4H. It is read/write addressable and has the following functions:

— Oscillator frequency divide-by value

After the main oscillator is activated, and the fxx/16 (the slowest clock speed) is selected as the CPU clock. If necessary, you can then increase the CPU clock speed fxx/8, fxx/2, or fxx/1.

System Clock Control Register (CLKCON)

D4H, Set 1, R/W

MSB

.7

.6

.5

.4

.3

.2

.1

.0

LSB

Not used (must keep always 0)

Not used (must keep always 0)

Divide-by selection bits for

CPU clock frequency:

00= fXX/16

01= fXX/8

10= fXX/2

11= fXX/1 (non-divided)

NOTE: The fxx can be generated by both main-system and sub-system oscillator therefore while main-system stops peripherals can be operated by sub-system.

Figure 7-4. System Clock Control Register (CLKCON)

7-3