Samsung S3C84E5 user manual Uart Timing Characteristics in Mode 0 10 MHz

ELECTRICAL DATAS3C84E5/C84E9/P84E9

	Table 17-10. UART Timing Characteristics in Mode 0 (10 MHz)
(TA = – 25 °C to + 85 °C, VDD = VLVR		to 5.5 V, Load capacitance = 80 pF)
	Parameter		Symbol	Min	Typ.	Max	Unit
	Serial port clock cycle time		tSCK	500	tCPU × 6	700	ns
	Output data setup to clock rising edge		tS1	300	tCPU × 5	–
	Clock rising edge to input data valid		tS2	–	–	300
	Output data hold after clock rising edge		tH1	tCPU – 50	tCPU	–
	Input data hold after clock rising edge		tH2	0	–	–
	Serial port clock High, Low level width		tHIGH, tLOW	200	tCPU × 3	400

NOTES:

1.All timings are in nanoseconds (ns) and assume a 10-MHz CPU clock frequency.

2.The unit tCPU means one CPU clock period.

	tSCK
tHIGH	tLOW
0.8 VDD
	0.2 VDD

Figure 17-7. Waveform for UART Timing Characteristics

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