Samsung S3C84E5 user manual Clkcon System Clock Control Register, D4H, Fxx/2, Fxx/1 non-divided

S3C84E5/C84E9/P84E9CONTROL REGISTER

CLKCON — System Clock Control Register D4H Set 1

Bit Identifier

Reset Value

Read/Write Addressing Mode

.7	.6	.5	.4	.3	.2	.1	.0
0	0	0	0	0	0	0	0
–	–	–	R/W	R/W	–	–	–

Register addressing mode only

.7–.5	Not used for the S3C84E5/C84E9/P84E9 (must keep always 0)
.4–.3	CPU Clock (System Clock) Selection Bits (note)
	0	0	fxx/16
	0	1	fxx/8
	1	0	fxx/2
	1	1	fxx/1 (non-divided)
.2–.0	Not used for the S3C84E5/C84E9/P84E9 (must keep always 0)

NOTE: After a reset, the slowest clock (divided by 16) is selected as the system clock. To select faster clock speeds, load the appropriate values to CLKCON.3 and CLKCON.4.

4-7