S3C84E5/C84E9/P84E9CONTROL REGISTER

IMR — Interrupt Mask Register

DDH

Set 1

Bit Identifier

Reset Value

Read/Write Addressing Mode

.7

.6

.7

.6

.5

.4

.3

.2

.1

.0

 

 

 

 

 

 

 

 

x

x

x

x

x

x

x

x

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

Register addressing mode only

Interrupt Level 7 (IRQ7) Enable Bit

0Disable (mask)

1Enable (un-mask)

Interrupt Level 6 (IRQ6) Enable Bit

0Disable (mask)

1Enable (un-mask)

.5

Interrupt Level 5 (IRQ5) Enable Bit

0Disable (mask)

1Enable (un-mask)

.4

Interrupt Level 4 (IRQ4) Enable Bit

0Disable (mask)

1Enable (un-mask)

.3

Interrupt Level 3 (IRQ3) Enable Bit

0Disable (mask)

1Enable (un-mask)

.2

Interrupt Level 2 (IRQ2) Enable Bit

0Disable (mask)

1Enable (un-mask)

.1

Interrupt Level 1 (IRQ1) Enable Bit

0Disable (mask)

1Enable (un-mask)

.0

Interrupt Level 0 (IRQ0) Enable Bit

0Disable (mask)

1Enable (un-mask)

NOTE: When an interrupt level is masked, any interrupt requests that may be issued are not recognized by the CPU.

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Image 78
Samsung S3C84E5 user manual IMR Interrupt Mask Register, Ddh