CONTROL REGISTERS S3C84E5/C84E9/P84E9
4-34
T1CON1 — Timer 1(1) Control Register E9H Set 1, Bank 1
Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0
Reset Value 0 0 0 0 0 0 0 0
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Addressing Mode Register addressing mode only
.7–.5 Timer 1(1) Input Clock Selection Bits
0 0 0 fxx/1024
0 0 1 fxx/256
0 1 0 fxx/64
0 1 1 fxx/8
1 0 0 fxx
1 0 1 External clock falling edge
1 1 0 External clock rising edge
1 1 1 Counter stop
.4–.3 Timer 1(1) Operating Mode Selection Bits
0 0 Interval mode
0 1 Capture mode (Capture on rising edge, OVF can occur)
1 0 Capture mode (Capture on falling edge, OVF can occur)
1 1 PWM mode
.2 Timer 1(1) Counter Enable Bit
0 No effect
1 Clear the timer 1(1) counter (Auto-clear bit)
.1 Timer 1(1) Match/Capture Interrupt Enable Bit
0 Disable interrupt
1 Enable interrupt
.0 Timer 1(1) Overflow Interrupt Enable
0 Disable overflow interrupt
1 Enable overflow interrupt