Samsung S3C84E5 user manual ADD Add, Format, Bytes Cycles Opcode

S3C84E5/C84E9/P84E9INSTRUCTION SET

ADD — Add

ADD	dst,src
Operation:	dst ← dst + src
	The source operand is added to the destination operand and the sum is stored in the destination.
	The contents of the source are unaffected. Two's-complement addition is performed.
Flags:	C: Set if there is a carry from the most significant bit of the result; cleared otherwise.
	Z: Set if the result is "0"; cleared otherwise.
	S: Set if the result is negative; cleared otherwise.
	V: Set if arithmetic overflow occurred, that is, if both operands are of the same sign and the
	result is of the opposite sign; cleared otherwise.
	D: Always cleared to "0".
	H: Set if a carry from the low-order nibble occurred.

Format:

opc dst src

opc src dst

Bytes	Cycles	Opcode	Addr Mode
		(Hex)	dst	src
2	4	02	r	r
	6	03	r	lr
3	6	04	R	R
		05	R	IR

opc

dst

src

3 6 06 R IM

Examples: Given: R1 = 12H, R2 = 03H, register 01H = 21H, register 02H = 03H, register 03H = 0AH:

ADD	R1,R2	→	R1	= 15H, R2 = 03H
ADD	R1,@R2	→	R1	= 1CH, R2 = 03H
ADD	01H,02H	→	Register 01H		=	24H, register 02H	=	03H
ADD	01H,@02H	→	Register 01H		=	2BH, register 02H	=	03H
ADD	01H,#25H	→	Register 01H		= 46H

In the first example, the destination working register R1 contains 12H and the source working register R2 contains 03H. The statement "ADD R1,R2" adds 03H to 12H, leaving the value 15H in the register R1.

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