Samsung S3C84E5 Incw Increment Word, Incw dst Operation dst ← dst +, 0FFH Incw RR0, Loop Incw RR0

S3C84E5/C84E9/P84E9 INSTRUCTION SET

INCW — Increment Word

INCW dst

Operation: dst ← dst + 1

The contents of the destination (which must be an even address) and the byte following that location are treated as a single 16-bit value that is incremented by one.

Flags:	C:	Unaffected.
	Z: Set if the result is "0"; cleared otherwise.
	S: Set if the result is negative; cleared otherwise.
	V: Set if arithmetic overflow occurred; cleared otherwise.
	D:	Unaffected.
	H:	Unaffected.
Format:
						Bytes	Cycles	Opcode		Addr Mode
								(Hex)		dst
		opc		dst		2	8		A0	RR
							8		A1	IR
Examples:	Given:		R0 = 1AH, R1		= 02H, register 02H = 0FH, and register 03H			=	0FFH:
	INCW			RR0	→	R0 = 1AH, R1 = 03H
	INCW			@R1	→	Register 02H = 10H, register 03H			= 00H
	In the first example, the working register pair RR0 contains the value 1AH in the register R0 and 02H
	in the register R1. The statement "INCW RR0" increments the 16-bit destination by one, leaving the
	value 03H in the register R1. In the second example, the statement "INCW								@R1" uses Indirect

Register (IR) addressing mode to increment the contents of the general register 03H from 0FFH to 00H and the register 02H from 0FH to 10H.

NOTE:A system malfunction may occur if you use a Zero (Z) flag (FLAGS.6) result together with an INCW instruction. To avoid this problem, it is recommended to use the INCW instruction as shown in the following example:

LOOP:	INCW	RR0
	LD	R2,R1
	OR	R2,R0
	JR	NZ,LOOP

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