USER’S MANUAL ERRATA S3C84E5/C84E9/P84E9
6
10. Table 17-8. Subsystem Oscillator (crystal) Stabilization Time (PAGE 17-7)
(TA = 25 °C)
Oscillator Test Condition Min Typ. Max Unit
Normal mode VDD = 4.5 V to 5.5 V – 800 1600 ms
VDD = VLVR to 3.3 V – 10 s
Strong mode VDD = 4.5 V to 5.5 V – 400 800 ms
VDD = VLVR to 3.3 V – 150 300
11. Table 17-9. Data Retention Supply Voltage in Stop Mode (PAGE 17-8)
(TA = – 25 °C to + 85 °C, VDD = VLVR to 5.5 V)
12. Table 17-10. UART Timing Characteristics in Mode 0 (PAGE 17-10)
(TA = – 25 °C to + 85 °C, VDD = VLVR to 5.5 V, Load capacitance = 80 pF)
Parameter Symbol Min Typ. Max Unit
Serial port clock cycle time tSCK 500 tCPU × 6 700 ns
Output data setup to clock rising edge tS1 300 tCPU × 5 –
Serial port clock High, Low level width tHIGH, tLOW 200 tCPU × 3 400