General Bus Architecture | Spectrum Brands C6x VME64 instruction

Monaco Technical Reference

Spectrum Signal Processing

Introduction

1.4.General Bus Architecture

The following block diagram shows the main components of the Monaco board.

'C6x Host Port Inteface (HPI)

	Node A	Node B		Node C	Node D	JTAG
	'C6x	'C6x		'C6x	'C6x
	PEM Site			PEM Site
DSP~LINK3 Interface		SBSRAM	SBSRAM			SBSRAM
DSP~LINK3 Interface		128K x 32	128K x 32			128K x 32
		SDRAM	SDRAM			SDRAM
SBSRAM	SDRAM	4M x 32	4M x 32			4M x 32
128K x 32	SDRAM
128K x 32	4M x 32
	4M x 32
PMC
Site
	Address Buffer	Address Buffer		Address Buffer	Address Buffer
	and	and		and	and
	Data Latches	Data Latches		Data Latches	Data Latches
PCI
Bus						Test Bus
Hurricane		Global Shared Bus				Controller
		Global Shared Bus
	Global Shared			SCV64	A24 VME
	SRAM			VME64		Slave
	512K x 32			Interface	Interface

VME P2 Connector

VME P1 Connector

Figure 1 Block Diagram

1.5.On-Board Power Supply

There is an on-board high-efficiency DC-DC power converter that supplies +2.5V and +3.3V power to the board from the VME 5V supply. The circuit efficiency is approximately 90%. The +3.3V supply is available to the PEM and PMC sites, as well as +5V and ±12V. Up to 16.5 Watts is available from the +3.3V supply for the PEM and PMC sites. The combined +3.3V current consumption of modules on these sites must not exceed 5 Amps.

When adding modules to the Monaco board, ensure that the power requirements for the modules are within the specified limits, and that the system power supply and cooling are sufficient to meet the added requirements.

4	Part Number 500-00191

Revision 2.00

Image 16

Spectrum Brands C6x VME64 manual General Bus Architecture, On-Board Power Supply

Contents

Monaco Revision Preface Iii Change Document Rev Date ChangesHistory Table of Contents Monaco Technical Reference Vii Viii List of Figures Table of Contents List of Tables Xii Introduction FeaturesProduct Operation Processors Interfaces VMEPMC PEM Reference Documents On-Board Power Supply General Bus Architecture Reset Conditions VME A24 Slave Interface ResetJtag Reset Sysreset Board Layout Board Layout Jumper Settings Description Jumper settingsOUT Part Number Processor Configurations Populated Processor Nodes Processor Node Block Diagram Internal Memory Processor Memory ConfigurationExternal Memory 0x0180 DSP Memory Map Address Nodes B, C, and D Synchronous Burst Sram Synchronous DramProcessor Expansion Module Host Port Processor Booting Processor Boot Source Jumpers Node Serial Port Routing Serial Port Routing PEM Connections for Serial Port 0 VME and PMC Connections for Serial Port Global Shared Bus Access Source Target Global Shared BusMemory Arbitration Single Cycle Bus Access Burst Cycle Bus Access Locked Cycles Global Shared Bus VME Operation VME64 Bus InterfaceSCV64 Primary Slave A32/A24 Interface Access A24 Secondary Slave Interface A24 Secondary Interface Memory Map HPI Register Addresses VME address Hpia Master A32/A24/A16 SCV64 Interface VME64 Bus Interface DSP~LINK3 Interface DSP~LINK3 Data Transfer Operating Modes Address Strobe Control Mode Astrben Interface Signals DSP~LINK3 Reset DSP~LINK3 Interface PCI Interface Hurricane ConfigurationPCI Offset Address Hurricane Register Set Value Initialize BCC2A Hurricane Implementation PCI Device Jtag Debugging Jtag Chain Jtag Debugging Interrupt Handling Overview DSP~LINK3 Interrupts to Node a Interrupt Routing PEM Interrupts PCI Bus InterruptsHurricane Interrupt SCV64 Interrupt Kipl Status Bits and the Iack Cycle KIPL2 KIPL1 KIPL0 Bus Error Interrupts Bit Node Whose Access Caused the Bus Error Inter-processor Interrupts VME Host Interrupts To Any Node Register Address Summary Access Privilege Bus Registers Vpage Register KFC2..0 KSIZE1..0 KADDR1..0 Vstatus Register Kavec BuserraKIPL2..0 Vinta Register Vintb Register Vintc Register Vintd Register Kipl Enable Register KiplendKiplenc Kiplenb DL3RESET DSP~LINK3 Register ID Register VME A24 Status Register HintaHintb Hintc VME A24 Control Register Registers Specifications Board IdentificationMonaco Monaco67 Specifications Parameter General Data Access/Transfer Performance Performance and Data Throughput Specifications Connector Pinouts Connector Layout VME Connectors VME P1 Connector Pinout VME P2 Connector Pinout PMC to VME P2 VME P2 Connector DSP~LINK3 to VME P2 PMC Connectors PMC Connector JN1 Pinout PMC Connector JN2 PMC Connector JN4 Non-standard PMC Connector JN5 PEM Connectors PEM 1 Connector Pinout PEM 2 Connector Pinout Jtag in Connector Pinout Jtag ConnectorsJtag OUT Connector Connector Pinouts Appendix a SCV64 Register Values SCV64 Register Initialization SCV64 Register Initialization Index VME Interrupts to node A, 40 register Reset Jtag Sysreset