DSP Memory Map | Spectrum Brands C6x VME64 manual

Spectrum Signal Processing	Monaco Technical Reference
	Processor Nodes

‘C6x Addr

0000 0000

0000 1000

0040 0000

0048 0000

0140 0000

Memory Contents

Internal-Program RAM

Reserved

Local SBSRAM

Reserved CE0

Memory Size

64 KB

4 MB - 64KB

512 KB

16 M - 512 KB

0180 0000

External-Memory Space CE1

Upon Reset

PEM EEPROM

Boot Mode

External-Memory Space CE1

After TOUT0 is toggled

DSP~LINK3

Shared SRAM

SCV64 Registers

(see the following CE1

memory map)

4 MB

01A0 0000

0200 0000

0300 0000

0400 0000

8000 0000

8001 0000

FFFF FFFF

Internal-Peripheral Space

Reserved

Local SDRAM CE2

Processor Expansion Module (PEM) CE3

Reserved

Internal-Data RAM

Reserved

2MB

6MB

16MB

16MB

2 GB - 64 MB

64 KB

2GB -

(2GB - 64 KB)

Figure 4 DSP Memory Map

Part Number 500-00191	13
Revision 2.00

Image 25

Spectrum Brands C6x VME64 manual DSP Memory Map

Contents

Monaco Revision Iii Preface Change Document Rev Date ChangesHistory Table of Contents Monaco Technical Reference Vii Viii List of Figures Table of Contents List of Tables Xii Introduction FeaturesProduct Operation Processors VME InterfacesPMC PEM Reference Documents General Bus Architecture On-Board Power Supply VME A24 Slave Interface Reset Reset ConditionsJtag Reset Sysreset Board Layout Board Layout Jumper Settings Description Jumper settingsOUT Part Number Processor Nodes Processor Configurations Populated Processor Node Block Diagram Internal Memory Processor Memory ConfigurationExternal Memory 0x0180 DSP Memory Map Nodes B, C, and D Address Synchronous Dram Synchronous Burst SramProcessor Expansion Module Host Port Processor Boot Source Jumpers Node Processor Booting Serial Port Routing Serial Port Routing VME and PMC Connections for Serial Port PEM Connections for Serial Port 0 Global Shared Bus Global Shared Bus Access Source TargetMemory Arbitration Burst Cycle Bus Access Single Cycle Bus Access Locked Cycles Global Shared Bus VME Operation VME64 Bus InterfaceSCV64 Primary Slave A32/A24 Interface A24 Secondary Slave Interface Access A24 Secondary Interface Memory Map Hpia HPI Register Addresses VME address Master A32/A24/A16 SCV64 Interface VME64 Bus Interface DSP~LINK3 Data Transfer Operating Modes DSP~LINK3 Interface Astrben Address Strobe Control Mode DSP~LINK3 Reset Interface Signals DSP~LINK3 Interface PCI Interface Hurricane ConfigurationPCI Offset Address Value Initialize Hurricane Register Set BCC2A PCI Device Hurricane Implementation Jtag Chain Jtag Debugging Jtag Debugging Overview Interrupt Handling Interrupt Routing DSP~LINK3 Interrupts to Node a PCI Bus Interrupts PEM InterruptsHurricane Interrupt SCV64 Interrupt KIPL2 KIPL1 KIPL0 Kipl Status Bits and the Iack Cycle Bit Node Whose Access Caused the Bus Error Bus Error Interrupts VME Host Interrupts To Any Node Inter-processor Interrupts Registers Register Address Summary Access Privilege Bus KFC2..0 KSIZE1..0 KADDR1..0 Vpage Register Vstatus Register Kavec BuserraKIPL2..0 Vinta Register Vintb Register Vintc Register Vintd Register Kiplend Kipl Enable RegisterKiplenc Kiplenb DSP~LINK3 Register DL3RESET ID Register Hinta VME A24 Status RegisterHintb Hintc VME A24 Control Register Registers Board Identification SpecificationsMonaco Monaco67 General Specifications Parameter Performance and Data Throughput Data Access/Transfer Performance Specifications Connector Layout Connector Pinouts VME P1 Connector Pinout VME Connectors VME P2 Connector Pinout PMC to VME P2 VME P2 Connector DSP~LINK3 to VME P2 PMC Connector JN1 Pinout PMC Connectors PMC Connector JN2 PMC Connector JN4 Non-standard PMC Connector JN5 PEM 1 Connector Pinout PEM Connectors PEM 2 Connector Pinout Jtag in Connector Pinout Jtag ConnectorsJtag OUT Connector Connector Pinouts SCV64 Register Initialization Appendix a SCV64 Register Values SCV64 Register Initialization VME Index Interrupts to node A, 40 register Reset Jtag Sysreset