Single Cycle Bus Access | Spectrum Brands C6x VME64 specification

Monaco Technical Reference

Spectrum Signal Processing

Global Shared Bus

Bus ownership is cycled between the two highest priority devices (SCV64 and Hurricane) until neither device requires the bus. Then the DSP Nodes are processed round robin. After one pass through the DSP chain, the cycle loops back to include the SCV64 and Hurricane. This eliminates any arbitration latency as bus ownership is transferred between devices, and grants the highest priority to those devices interfacing to external buses (VME and PCI), which require the fastest response. The arbitration cycle is shown in the following figure.

Note: Because there is no ownership timer for either Hurricane or SCV64 chip the system designer must ensure that processors are not held off from the shared resources for unreasonable lengths of time.

Highest Priority Lowest priority

SCV64	Hurricane	Node A	Node B	Node C	Node D
Round Robin
VME & PCI Bus				DSP

Round Robin

Figure 7 Global Bus Arbitration

Access to the Global Shared Bus can use single, burst, or locked cycles.

3.2.1.Single Cycle Bus Access

For single cycle accesses a device requests the global shared bus by simply initiating a read or write access to the bus. When the bus is free, the device acquires it and performs the single cycle access. The bus is then released.

3.2.2.Burst Cycle Bus Access

Burst cycles are used during DMA transfers from a ‘C6x processor to the Global Shared Bus. A 6-bit bus ownership timer on each node prevents a ‘C6x from owning the bus for more than 640 ns when another device is requesting the bus. When the burst cycles are begun, the timer is started. If another device requests the bus when the timer expires, the bus is released; otherwise ownership is maintained and the timer is reset and started again.

If multiple DSPs request the bus, this scheme allocates time to them fairly so that none are locked out.

20	Part Number 500-00191
	Revision 2.00

Image 32

Spectrum Brands C6x VME64 manual Single Cycle Bus Access, Burst Cycle Bus Access

Contents

Monaco Revision Preface Iii History Document Rev Date ChangesChange Table of Contents Monaco Technical Reference Vii Viii List of Figures Table of Contents List of Tables Xii Product Operation Processors FeaturesIntroduction Interfaces VMEPMC PEM Reference Documents On-Board Power Supply General Bus Architecture Reset Conditions VME A24 Slave Interface ResetJtag Reset Sysreset Board Layout Board Layout OUT Jumper settingsJumper Settings Description Part Number Processor Configurations Populated Processor Nodes Processor Node Block Diagram External Memory Processor Memory ConfigurationInternal Memory 0x0180 DSP Memory Map Address Nodes B, C, and D Synchronous Burst Sram Synchronous DramProcessor Expansion Module Host Port Processor Booting Processor Boot Source Jumpers Node Serial Port Routing Serial Port Routing PEM Connections for Serial Port 0 VME and PMC Connections for Serial Port Global Shared Bus Access Source Target Global Shared BusMemory Arbitration Single Cycle Bus Access Burst Cycle Bus Access Locked Cycles Global Shared Bus SCV64 Primary Slave A32/A24 Interface VME64 Bus InterfaceVME Operation Access A24 Secondary Slave Interface A24 Secondary Interface Memory Map HPI Register Addresses VME address Hpia Master A32/A24/A16 SCV64 Interface VME64 Bus Interface DSP~LINK3 Interface DSP~LINK3 Data Transfer Operating Modes Address Strobe Control Mode Astrben Interface Signals DSP~LINK3 Reset DSP~LINK3 Interface PCI Offset Address Hurricane ConfigurationPCI Interface Hurricane Register Set Value Initialize BCC2A Hurricane Implementation PCI Device Jtag Debugging Jtag Chain Jtag Debugging Interrupt Handling Overview DSP~LINK3 Interrupts to Node a Interrupt Routing PEM Interrupts PCI Bus InterruptsHurricane Interrupt SCV64 Interrupt Kipl Status Bits and the Iack Cycle KIPL2 KIPL1 KIPL0 Bus Error Interrupts Bit Node Whose Access Caused the Bus Error Inter-processor Interrupts VME Host Interrupts To Any Node Register Address Summary Access Privilege Bus Registers Vpage Register KFC2..0 KSIZE1..0 KADDR1..0 Vstatus Register KIPL2..0 BuserraKavec Vinta Register Vintb Register Vintc Register Vintd Register Kipl Enable Register KiplendKiplenc Kiplenb DL3RESET DSP~LINK3 Register ID Register VME A24 Status Register HintaHintb Hintc VME A24 Control Register Registers Specifications Board IdentificationMonaco Monaco67 Specifications Parameter General Data Access/Transfer Performance Performance and Data Throughput Specifications Connector Pinouts Connector Layout VME Connectors VME P1 Connector Pinout VME P2 Connector Pinout PMC to VME P2 VME P2 Connector DSP~LINK3 to VME P2 PMC Connectors PMC Connector JN1 Pinout PMC Connector JN2 PMC Connector JN4 Non-standard PMC Connector JN5 PEM Connectors PEM 1 Connector Pinout PEM 2 Connector Pinout Jtag OUT Connector Jtag ConnectorsJtag in Connector Pinout Connector Pinouts Appendix a SCV64 Register Values SCV64 Register Initialization SCV64 Register Initialization Index VME Interrupts to node A, 40 register Reset Jtag Sysreset