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Spectrum Brands C6x VME64 Synchronous Burst Sram, Synchronous Dram, Processor Expansion Module

Models: C6x VME64

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Spectrum Signal Processing	Monaco Technical Reference
	Processor Nodes

2.2.Synchronous Burst SRAM

The board provides 128K of 32-bit synchronous burst SRAM (SBSRAM) on each ‘C6x local bus. The Monaco board supports 1 wait state operation.

2.3.Synchronous DRAM

The board provides 4M of 32-bit synchronous DRAM on each ‘C6x bus. The Monaco board supports 1 wait state operation. An additional 4M of 32-bit synchronous DRAM per DSP can also be supported on a PEM module.

Burst data transfer rates from CPU to SDRAM are 400 Mbytes/s on a Monaco with 200 MHz TMS320C6201 chips.

2.4.Processor Expansion Module

The Processor Expansion Module (PEM) provides a simple and flexible interface from the DSP to I/O. It is similar to a PMC module, although physically narrower.

The Monaco board is designed to support two DSPs per PEM site, with a pair of connectors for each DSP. While both DSP devices share the same PEM, the two DSP buses are kept separate to allow very fast PEM data transfer rates.

The PEM is capable of booting the DSPs from local ROM, with up to 4 MBytes of addressable boot space available to each DSP.

Refer to the PEM Specification for mechanical and functional details of the PEM interface.

2.5.Host Port

A separate A24 VMEbus Slave interface is used for direct access to the DSP’s Host Port Interface. This interface can be used for downloading code and as a control path from the host to the DSP. Data transfer rates depend upon both the code executing in the DSP and the VMEbus Master performing the transfers, but can be as high as 30 Mbytes/second.

Jumper block JP1 selects the VME A24 base address for this slave interface.

2.6.Interrupt Lines

There are four external interrupt inputs on each ‘C6x. They are INT4, INT5, INT6, and INT7. All four must be configured as rising-edge triggered interrupts upon initialization. See the Interrupt Handling chapter for further information.

Part Number 500-00191	15
Revision 2.00

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Spectrum Brands C6x VME64 Synchronous Burst Sram, Synchronous Dram, Processor Expansion Module, Host Port, Interrupt Lines

Contents

Monaco Revision Iii PrefaceDocument Rev Date Changes ChangeHistory Table of Contents Monaco Technical Reference Vii Viii List of Figures Table of Contents List of Tables Xii Features IntroductionProduct Operation Processors PEM InterfacesVME PMCReference Documents General Bus Architecture On-Board Power SupplySysreset Reset ConditionsVME A24 Slave Interface Reset Jtag ResetBoard Layout Board LayoutJumper settings Jumper Settings DescriptionOUT Part Number Processor Nodes Processor Configurations PopulatedProcessor Node Block Diagram Processor Memory Configuration Internal MemoryExternal Memory 0x0180 DSP Memory Map Nodes B, C, and D AddressHost Port Synchronous Burst SramSynchronous Dram Processor Expansion ModuleProcessor Boot Source Jumpers Node Processor BootingSerial Port Routing Serial Port RoutingVME and PMC Connections for Serial Port PEM Connections for Serial Port 0Arbitration Global Shared Bus Access Source TargetGlobal Shared Bus MemoryBurst Cycle Bus Access Single Cycle Bus AccessLocked Cycles Global Shared Bus VME64 Bus Interface VME OperationSCV64 Primary Slave A32/A24 Interface A24 Secondary Slave Interface AccessA24 Secondary Interface Memory Map Hpia HPI Register Addresses VME addressMaster A32/A24/A16 SCV64 Interface VME64 Bus Interface DSP~LINK3 Data Transfer Operating Modes DSP~LINK3 InterfaceAstrben Address Strobe Control ModeDSP~LINK3 Reset Interface SignalsDSP~LINK3 Interface Hurricane Configuration PCI InterfacePCI Offset Address Value Initialize Hurricane Register SetBCC2A PCI Device Hurricane ImplementationJtag Chain Jtag DebuggingJtag Debugging Overview Interrupt HandlingInterrupt Routing DSP~LINK3 Interrupts to Node aSCV64 Interrupt PEM InterruptsPCI Bus Interrupts Hurricane InterruptKIPL2 KIPL1 KIPL0 Kipl Status Bits and the Iack CycleBit Node Whose Access Caused the Bus Error Bus Error InterruptsVME Host Interrupts To Any Node Inter-processor InterruptsRegisters Register Address Summary Access Privilege BusKFC2..0 KSIZE1..0 KADDR1..0 Vpage RegisterVstatus Register Buserra KavecKIPL2..0 Vinta Register Vintb Register Vintc Register Vintd Register Kiplenb Kipl Enable RegisterKiplend KiplencDSP~LINK3 Register DL3RESETID Register Hintc VME A24 Status RegisterHinta HintbVME A24 Control Register Registers Monaco67 SpecificationsBoard Identification MonacoGeneral Specifications ParameterPerformance and Data Throughput Data Access/Transfer PerformanceSpecifications Connector Layout Connector PinoutsVME P1 Connector Pinout VME ConnectorsVME P2 Connector Pinout PMC to VME P2 VME P2 Connector DSP~LINK3 to VME P2 PMC Connector JN1 Pinout PMC ConnectorsPMC Connector JN2 PMC Connector JN4 Non-standard PMC Connector JN5 PEM 1 Connector Pinout PEM ConnectorsPEM 2 Connector Pinout Jtag Connectors Jtag in Connector PinoutJtag OUT Connector Connector Pinouts SCV64 Register Initialization Appendix a SCV64 Register ValuesSCV64 Register Initialization VME IndexInterrupts to node A, 40 register Reset Jtag Sysreset