Vii | Spectrum Brands C6x VME64 specification

Spectrum Signal Processing	Monaco Technical Reference
	Table of Contents
DSP~LINK3 Register	54
ID Register	55
VME A24 Status Register	56
VME A24 Control Register	57
10 Specifications	59
10.1. Board Identification	59
10.2. General	60
10.3. Performance and Data Throughput	61
11 Connector Pinouts	63
11.1. VME Connectors	64
11.2. PMC Connectors	67
11.3. PEM Connectors	71
11.4. JTAG Connectors	73

Part Number 500-00191	vii
Revision 2.00

Image 7

Spectrum Brands C6x VME64 manual Vii

Contents

Monaco Revision Iii Preface Change Document Rev Date ChangesHistory Table of Contents Monaco Technical Reference Vii Viii List of Figures Table of Contents List of Tables Xii Introduction FeaturesProduct Operation Processors PEM InterfacesVME PMC Reference Documents General Bus Architecture On-Board Power Supply Sysreset Reset ConditionsVME A24 Slave Interface Reset Jtag Reset Board Layout Board Layout Jumper Settings Description Jumper settingsOUT Part Number Processor Nodes Processor Configurations Populated Processor Node Block Diagram Internal Memory Processor Memory ConfigurationExternal Memory 0x0180 DSP Memory Map Nodes B, C, and D Address Host Port Synchronous Burst SramSynchronous Dram Processor Expansion Module Processor Boot Source Jumpers Node Processor Booting Serial Port Routing Serial Port Routing VME and PMC Connections for Serial Port PEM Connections for Serial Port 0 Arbitration Global Shared Bus Access Source TargetGlobal Shared Bus Memory Burst Cycle Bus Access Single Cycle Bus Access Locked Cycles Global Shared Bus VME Operation VME64 Bus InterfaceSCV64 Primary Slave A32/A24 Interface A24 Secondary Slave Interface Access A24 Secondary Interface Memory Map Hpia HPI Register Addresses VME address Master A32/A24/A16 SCV64 Interface VME64 Bus Interface DSP~LINK3 Data Transfer Operating Modes DSP~LINK3 Interface Astrben Address Strobe Control Mode DSP~LINK3 Reset Interface Signals DSP~LINK3 Interface PCI Interface Hurricane ConfigurationPCI Offset Address Value Initialize Hurricane Register Set BCC2A PCI Device Hurricane Implementation Jtag Chain Jtag Debugging Jtag Debugging Overview Interrupt Handling Interrupt Routing DSP~LINK3 Interrupts to Node a SCV64 Interrupt PEM InterruptsPCI Bus Interrupts Hurricane Interrupt KIPL2 KIPL1 KIPL0 Kipl Status Bits and the Iack Cycle Bit Node Whose Access Caused the Bus Error Bus Error Interrupts VME Host Interrupts To Any Node Inter-processor Interrupts Registers Register Address Summary Access Privilege Bus KFC2..0 KSIZE1..0 KADDR1..0 Vpage Register Vstatus Register Kavec BuserraKIPL2..0 Vinta Register Vintb Register Vintc Register Vintd Register Kiplenb Kipl Enable RegisterKiplend Kiplenc DSP~LINK3 Register DL3RESET ID Register Hintc VME A24 Status RegisterHinta Hintb VME A24 Control Register Registers Monaco67 SpecificationsBoard Identification Monaco General Specifications Parameter Performance and Data Throughput Data Access/Transfer Performance Specifications Connector Layout Connector Pinouts VME P1 Connector Pinout VME Connectors VME P2 Connector Pinout PMC to VME P2 VME P2 Connector DSP~LINK3 to VME P2 PMC Connector JN1 Pinout PMC Connectors PMC Connector JN2 PMC Connector JN4 Non-standard PMC Connector JN5 PEM 1 Connector Pinout PEM Connectors PEM 2 Connector Pinout Jtag in Connector Pinout Jtag ConnectorsJtag OUT Connector Connector Pinouts SCV64 Register Initialization Appendix a SCV64 Register Values SCV64 Register Initialization VME Index Interrupts to node A, 40 register Reset Jtag Sysreset