Spectrum Signal Processing Monaco Technical Reference
Table of Contents
Part Number 500-00191 v
Revision 2.00
Table of Contents

1 Introduction..............................................................................................................................1

1.1. Features....................................................................................................................................1
1.2. Interfaces.................................................................................................................................. 2
1.2.1. VME.............................................................................................................................2
1.2.2. PMC............................................................................................................................ 2
1.2.3. PEM.............................................................................................................................2
1.2.4. Serial Ports..................................................................................................................2
1.2.5. JTAG........................................................................................................................... 2
1.3. Reference Documents.............................................................................................................. 3
1.4. General Bus Architecture..........................................................................................................4
1.5. On-Board Power Supply........................................................................................................... 4
1.6. Reset Conditions.......................................................................................................................5
1.6.1. VME SYSRESET........................................................................................................ 5
1.6.2. VME A24 Slave Interface Reset..................................................................................5
1.6.3. JTAG Reset.................................................................................................................5
1.7. Board Layout.............................................................................................................................6
1.8. Jumper settings.........................................................................................................................7

2 Processor Nodes.....................................................................................................................9

2.1. Processor Memory Configuration ...........................................................................................11
2.1.1. Internal Memory........................................................................................................ 11
2.1.2. External Memory....................................................................................................... 11
2.2. Synchronous Burst SRAM...................................................................................................... 15
2.3. Synchronous DRAM ...............................................................................................................15
2.4. Processor Expansion Module.................................................................................................15
2.5. Host Port................................................................................................................................. 15
2.6. Interrupt Lines......................................................................................................................... 15
2.7. Processor Booting...................................................................................................................16
2.8. Serial Port Routing..................................................................................................................17

3 Global Shared Bus ............................................................................................................ ....19

3.1. Memory................................................................................................................................... 19
3.2. Arbitration................................................................................................................................19
3.2.1. Single Cycle Bus Access ..........................................................................................20
3.2.2. Burst Cycle Bus Access............................................................................................20