Spectrum Brands C6x VME64 manual PEM Interrupts, PCI Bus Interrupts, Hurricane Interrupt, Bit

Spectrum Signal Processing	Monaco Technical Reference
	Interrupt Handling

8.3.PEM Interrupts

There are two active-low, driven interrupts from the PEM connectors for each node. These interrupts (/PEM INT1 and /PEM INT2) are OR’ed together. Their output is routed to INT6 of each node’s DSP and inverted to create a rising-edge trigger.

The Monaco board does not latch the PEM interrupts. They must be cleared on the PEM module that generated them.

8.4.PCI Bus Interrupts

The four active-low interrupt signals from the PCI bus (INTA#, INTB#, INTC#, and INTD#) are physically tied together and routed to INT5 of each of ‘C6x DSPs. They are also buffered through a de-bounce circuit because they are open-collector. On node A the PCI bus interrupt is also shared with the Hurricane interrupt on INT5 of the ‘C6x through an OR gate.

The interrupt is not latched, and its source must be cleared on the PMC module.

8.5.Hurricane Interrupt

The interrupt signal from the Hurricane chip is routed to each of the board’s ‘C6x processors. On node A the PCI bus interrupt is also shared with the Hurricane interrupt on INT5 of the ‘C6x through an OR gate. For nodes B, C, and D, the Hurricane interrupt is routed to INT7 of the ‘C6x.

8.6.SCV64 Interrupt

An interrupt line from the SCV64 VME interface is routed to the INT4 interrupt input of all four ‘C6x processors. The interrupt provides VME, SCV64 timers and DMA, and other local interrupt capability. On-board logic routes VME bus error and the inter- processor VINTx interrupts to INT4 as well.

This interrupt can be individually enabled or disabled for each node using the

KIPL Enable Register (address 016D 8014h). Bits D0..D4 enable the interrupt for each node when set to “1”. The SCV64 interrupt is disabled from reaching the node when the corresponding bit is set to “0”.

Bit	Interrupted Node
D0	Node A
D1	Node B
D2	Node C
D3	Node D

Part Number 500-00191	41
Revision 2.00