Buserra, Kavec, KIPL2..0 | Spectrum Brands C6x VME64 manual

Monaco Technical Reference		Spectrum Signal Processing
Registers

		on reset.

	BUSERRA	Status of the last bus cycle access made to the SCV64 by node A, including
		SCV64 register and VME master accesses. Set to “1” if there was an error.
		Cleared by writing “10h” to the VSTATUS register. All other interrupts are
		cleared when the source of the interrupt is cleared. This interrupt is cleared
		on reset.

	KAVEC	Status of the interrupt vector last received on the data bus. High if the
		vector was not valid. During the IACK cycle, a non-vectored interrupt
		source causes this bit to be set, denoting a non-valid vector value on the
		bus. This bit is cleared on reset. The next SCV64 register, IACK, or
		VMEOUT cycle updates KAVEC. This signal is active high.

	/KIPL2..0	The interrupt level of pending interrupts in the SCV64. These signals are
		active low. For example, a value of 0x0 indicates that interrupt level 7 is
		pending.

48	Part Number 500-00191
	Revision 2.00

Image 60

Spectrum Brands C6x VME64 manual Buserra, Kavec, KIPL2..0

Contents

Monaco Revision Preface Iii Document Rev Date Changes ChangeHistory Table of Contents Monaco Technical Reference Vii Viii List of Figures Table of Contents List of Tables Xii Features IntroductionProduct Operation Processors Interfaces VMEPMC PEM Reference Documents On-Board Power Supply General Bus Architecture Reset Conditions VME A24 Slave Interface ResetJtag Reset Sysreset Board Layout Board Layout Jumper settings Jumper Settings DescriptionOUT Part Number Processor Configurations Populated Processor Nodes Processor Node Block Diagram Processor Memory Configuration Internal MemoryExternal Memory 0x0180 DSP Memory Map Address Nodes B, C, and D Synchronous Burst Sram Synchronous DramProcessor Expansion Module Host Port Processor Booting Processor Boot Source Jumpers Node Serial Port Routing Serial Port Routing PEM Connections for Serial Port 0 VME and PMC Connections for Serial Port Global Shared Bus Access Source Target Global Shared BusMemory Arbitration Single Cycle Bus Access Burst Cycle Bus Access Locked Cycles Global Shared Bus VME64 Bus Interface VME OperationSCV64 Primary Slave A32/A24 Interface Access A24 Secondary Slave Interface A24 Secondary Interface Memory Map HPI Register Addresses VME address Hpia Master A32/A24/A16 SCV64 Interface VME64 Bus Interface DSP~LINK3 Interface DSP~LINK3 Data Transfer Operating Modes Address Strobe Control Mode Astrben Interface Signals DSP~LINK3 Reset DSP~LINK3 Interface Hurricane Configuration PCI InterfacePCI Offset Address Hurricane Register Set Value Initialize BCC2A Hurricane Implementation PCI Device Jtag Debugging Jtag Chain Jtag Debugging Interrupt Handling Overview DSP~LINK3 Interrupts to Node a Interrupt Routing PEM Interrupts PCI Bus InterruptsHurricane Interrupt SCV64 Interrupt Kipl Status Bits and the Iack Cycle KIPL2 KIPL1 KIPL0 Bus Error Interrupts Bit Node Whose Access Caused the Bus Error Inter-processor Interrupts VME Host Interrupts To Any Node Register Address Summary Access Privilege Bus Registers Vpage Register KFC2..0 KSIZE1..0 KADDR1..0 Vstatus Register Buserra KavecKIPL2..0 Vinta Register Vintb Register Vintc Register Vintd Register Kipl Enable Register KiplendKiplenc Kiplenb DL3RESET DSP~LINK3 Register ID Register VME A24 Status Register HintaHintb Hintc VME A24 Control Register Registers Specifications Board IdentificationMonaco Monaco67 Specifications Parameter General Data Access/Transfer Performance Performance and Data Throughput Specifications Connector Pinouts Connector Layout VME Connectors VME P1 Connector Pinout VME P2 Connector Pinout PMC to VME P2 VME P2 Connector DSP~LINK3 to VME P2 PMC Connectors PMC Connector JN1 Pinout PMC Connector JN2 PMC Connector JN4 Non-standard PMC Connector JN5 PEM Connectors PEM 1 Connector Pinout PEM 2 Connector Pinout Jtag Connectors Jtag in Connector PinoutJtag OUT Connector Connector Pinouts Appendix a SCV64 Register Values SCV64 Register Initialization SCV64 Register Initialization Index VME Interrupts to node A, 40 register Reset Jtag Sysreset