Bus Error Interrupts | Spectrum Brands C6x VME64 manual

Spectrum Signal Processing	Monaco Technical Reference
	Interrupt Handling

SCV64 interrupts can be generated from the VMEbus (vectored) or internally by the

SCV64 (auto-vectored).

∙If the interrupt was caused by an external VMEbus interrupt the SCV64 initiates an /IACK cycle on the VMEbus. The /IACK cycle is acknowledged by the interrupter which puts its interrupt vector on the lower 8 data bits of the DSP’s data bus.

∙If the /KIPL lines were set due to an internal (auto-vectored) interrupt source the SCV64 initiates an /IACK cycle on the VMEbus, but no value is place on the lower 8 data bits. The SCV64 terminates the cycle by asserting the /KAVEC signal.

The KAVEC bit (bit D3) in the VSTATUS Register can be read to determine which type of interrupt was generated. After an IACK cycle is performed, it is set to “0” if the value on the lower 8 bits is a valid interrupt vector; or to “1” if the value is not a valid interrupt vector.

Auto-vectored interrupt sources can be cleared by accessing the SCV64 register set.

Refer to the SCV64 User Manual for more information.

8.7.Bus Error Interrupts

Bus error interrupts (BUSERR_x) are generated whenever an access cycle from a node or SCV64 DMA to the VME bus causes the SCV64 to generate a bus error.

This interrupt is routed only to INT4 of the ‘C6x responsible for causing the VME bus error. On-board logic routes enabled SCV64 interrupts and the inter-processor VINTx interrupts to INT4 as well.

Any node can also determine the status of the bus error interrupts by reading the VSTATUS Register at address 016D 8000h. A “1” in any of the following bit positions of the register indicates which nodes have pending bus error interrupts.

Bit Node Whose Access Caused the Bus Error

D4 Node A

D5 Node B

D6 Node C

D7 Node D

To clear the interrupt, the interrupted ‘C6x writes a “1” to the same bit in the VSTATUS Register. It must also clear the appropriate bits in the SCV64 DCSR register before the board can access the VME bus again.

Part Number 500-00191	43
Revision 2.00

Image 55

Spectrum Brands C6x VME64 manual Bus Error Interrupts, Bit Node Whose Access Caused the Bus Error

Contents

Monaco Revision Iii Preface Change Document Rev Date ChangesHistory Table of Contents Monaco Technical Reference Vii Viii List of Figures Table of Contents List of Tables Xii Introduction FeaturesProduct Operation Processors PEM InterfacesVME PMC Reference Documents General Bus Architecture On-Board Power Supply Sysreset Reset ConditionsVME A24 Slave Interface Reset Jtag Reset Board Layout Board Layout Jumper Settings Description Jumper settingsOUT Part Number Processor Nodes Processor Configurations Populated Processor Node Block Diagram Internal Memory Processor Memory ConfigurationExternal Memory 0x0180 DSP Memory Map Nodes B, C, and D Address Host Port Synchronous Burst SramSynchronous Dram Processor Expansion Module Processor Boot Source Jumpers Node Processor Booting Serial Port Routing Serial Port Routing VME and PMC Connections for Serial Port PEM Connections for Serial Port 0 Arbitration Global Shared Bus Access Source TargetGlobal Shared Bus Memory Burst Cycle Bus Access Single Cycle Bus Access Locked Cycles Global Shared Bus VME Operation VME64 Bus InterfaceSCV64 Primary Slave A32/A24 Interface A24 Secondary Slave Interface Access A24 Secondary Interface Memory Map Hpia HPI Register Addresses VME address Master A32/A24/A16 SCV64 Interface VME64 Bus Interface DSP~LINK3 Data Transfer Operating Modes DSP~LINK3 Interface Astrben Address Strobe Control Mode DSP~LINK3 Reset Interface Signals DSP~LINK3 Interface PCI Interface Hurricane ConfigurationPCI Offset Address Value Initialize Hurricane Register Set BCC2A PCI Device Hurricane Implementation Jtag Chain Jtag Debugging Jtag Debugging Overview Interrupt Handling Interrupt Routing DSP~LINK3 Interrupts to Node a SCV64 Interrupt PEM InterruptsPCI Bus Interrupts Hurricane Interrupt KIPL2 KIPL1 KIPL0 Kipl Status Bits and the Iack Cycle Bit Node Whose Access Caused the Bus Error Bus Error Interrupts VME Host Interrupts To Any Node Inter-processor Interrupts Registers Register Address Summary Access Privilege Bus KFC2..0 KSIZE1..0 KADDR1..0 Vpage Register Vstatus Register Kavec BuserraKIPL2..0 Vinta Register Vintb Register Vintc Register Vintd Register Kiplenb Kipl Enable RegisterKiplend Kiplenc DSP~LINK3 Register DL3RESET ID Register Hintc VME A24 Status RegisterHinta Hintb VME A24 Control Register Registers Monaco67 SpecificationsBoard Identification Monaco General Specifications Parameter Performance and Data Throughput Data Access/Transfer Performance Specifications Connector Layout Connector Pinouts VME P1 Connector Pinout VME Connectors VME P2 Connector Pinout PMC to VME P2 VME P2 Connector DSP~LINK3 to VME P2 PMC Connector JN1 Pinout PMC Connectors PMC Connector JN2 PMC Connector JN4 Non-standard PMC Connector JN5 PEM 1 Connector Pinout PEM Connectors PEM 2 Connector Pinout Jtag in Connector Pinout Jtag ConnectorsJtag OUT Connector Connector Pinouts SCV64 Register Initialization Appendix a SCV64 Register Values SCV64 Register Initialization VME Index Interrupts to node A, 40 register Reset Jtag Sysreset