A24 Secondary Interface Memory Map | Spectrum Brands C6x VME64

Spectrum Signal Processing	Monaco Technical Reference
	VME64 Bus Interface

VME Offset Address

00 0000h

00 0FFFh

00 1000h

00 1003h

00 1004h

00 1007h

00 1008h

00 1FFFh

00 2000h

00 2FFFh

00 3000h

00 3FFFh

00 4000h

00 4FFFh

00 5000h

00 5FFFh

00 6000h

00 FFFFh

01 0000h

01 3FFCh

01 4000h

01 3FFCh

01 B000h

01 3FFCh

01 C000h

01 FFFCh

Test Bus Controller Registers (JTAG)

VME A24 Status Register (Read Only)

VME A24 Control Register (Read/Write)

Reserved

Node A HPI Registers

Node B HPI Registers

Node C HPI Registers

Node D HPI Registers

Reserved

Node A HPID DMA Space (HPIA incremented)

all addresses mapped to 00 2008h

Node B HPID DMA Space (HPIA incremented)

all addresses mapped to 00 3008h

Node C HPID DMA Space (HPIA incremented)

all addresses mapped to 00 4008h

Node D HPID DMA Space (HPIA incremented)

all addresses mapped to 00 5008h

16KB

16KB

16KB

16KB

FPGA

‘C6x

‘C6x

Figure 9 A24 Secondary Interface Memory Map

Refer to the JTAG Debugging chapter for information on using the Test Bus Controller for JTAG operation. The VME A24 Status Register and the

VME A24 Control Register are described in the Registers chapter.

Part Number 500-00191	25
Revision 2.00

Image 37

Spectrum Brands C6x VME64 manual A24 Secondary Interface Memory Map

Contents

Monaco Revision Iii Preface Change Document Rev Date ChangesHistory Table of Contents Monaco Technical Reference Vii Viii List of Figures Table of Contents List of Tables Xii Introduction FeaturesProduct Operation Processors VME InterfacesPMC PEM Reference Documents General Bus Architecture On-Board Power Supply VME A24 Slave Interface Reset Reset ConditionsJtag Reset Sysreset Board Layout Board Layout Jumper Settings Description Jumper settingsOUT Part Number Processor Nodes Processor Configurations Populated Processor Node Block Diagram Internal Memory Processor Memory ConfigurationExternal Memory 0x0180 DSP Memory Map Nodes B, C, and D Address Synchronous Dram Synchronous Burst SramProcessor Expansion Module Host Port Processor Boot Source Jumpers Node Processor Booting Serial Port Routing Serial Port Routing VME and PMC Connections for Serial Port PEM Connections for Serial Port 0 Global Shared Bus Global Shared Bus Access Source TargetMemory Arbitration Burst Cycle Bus Access Single Cycle Bus Access Locked Cycles Global Shared Bus VME Operation VME64 Bus InterfaceSCV64 Primary Slave A32/A24 Interface A24 Secondary Slave Interface Access A24 Secondary Interface Memory Map Hpia HPI Register Addresses VME address Master A32/A24/A16 SCV64 Interface VME64 Bus Interface DSP~LINK3 Data Transfer Operating Modes DSP~LINK3 Interface Astrben Address Strobe Control Mode DSP~LINK3 Reset Interface Signals DSP~LINK3 Interface PCI Interface Hurricane ConfigurationPCI Offset Address Value Initialize Hurricane Register Set BCC2A PCI Device Hurricane Implementation Jtag Chain Jtag Debugging Jtag Debugging Overview Interrupt Handling Interrupt Routing DSP~LINK3 Interrupts to Node a PCI Bus Interrupts PEM InterruptsHurricane Interrupt SCV64 Interrupt KIPL2 KIPL1 KIPL0 Kipl Status Bits and the Iack Cycle Bit Node Whose Access Caused the Bus Error Bus Error Interrupts VME Host Interrupts To Any Node Inter-processor Interrupts Registers Register Address Summary Access Privilege Bus KFC2..0 KSIZE1..0 KADDR1..0 Vpage Register Vstatus Register Kavec BuserraKIPL2..0 Vinta Register Vintb Register Vintc Register Vintd Register Kiplend Kipl Enable RegisterKiplenc Kiplenb DSP~LINK3 Register DL3RESET ID Register Hinta VME A24 Status RegisterHintb Hintc VME A24 Control Register Registers Board Identification SpecificationsMonaco Monaco67 General Specifications Parameter Performance and Data Throughput Data Access/Transfer Performance Specifications Connector Layout Connector Pinouts VME P1 Connector Pinout VME Connectors VME P2 Connector Pinout PMC to VME P2 VME P2 Connector DSP~LINK3 to VME P2 PMC Connector JN1 Pinout PMC Connectors PMC Connector JN2 PMC Connector JN4 Non-standard PMC Connector JN5 PEM 1 Connector Pinout PEM Connectors PEM 2 Connector Pinout Jtag in Connector Pinout Jtag ConnectorsJtag OUT Connector Connector Pinouts SCV64 Register Initialization Appendix a SCV64 Register Values SCV64 Register Initialization VME Index Interrupts to node A, 40 register Reset Jtag Sysreset