PMC Connector JN4 | Spectrum Brands C6x VME64 instruction

Spectrum Signal Processing	Monaco Technical Reference
	Connector Pinouts

Table 21 PMC Connector JN4

Pin #	Signal	Pin #	Signal

1	P2C1	2	P2A1

3	P2C2	4	P2A2

5	P2C3	6	P2A3

7	P2C4	8	P2A4

9	P2C5	10	P2A5

11	P2C6	12	P2A6

13	P2C7	14	P2A7

15	P2C8	16	P2A8

17	P2C9	18	P2A9

19	P2C10	20	P2A10

21	P2C11	22	P2A11

23	P2C12	24	P2A12

25	P2C13	26	P2A13

27	P2C14	28	P2A14

29	P2C15	30	P2A15

31	P2C16	32	P2A16

33	P2C17	34	P2A17

35	P2C18	36	P2A18

37	P2C19	38	P2A19

39	P2C20	40	P2A20

41	P2C21	42	P2A21

43	P2C22	44	P2A22

45	P2C23	46	P2A23

47	P2C24	48	P2A24

49	P2C25	50	P2A25

51	P2C26	52	P2A26

53	P2C27	54	P2A27

55	P2C28	56	P2A28

57	P2C29	58	P2A29

59	P2C30	60	P2A30

61	P2C31	62	P2A31

63	P2C32	64	P2A32

Part Number 500-00191	69
Revision 2.00

Image 81

Spectrum Brands C6x VME64 manual PMC Connector JN4

Contents

Monaco Revision Iii Preface Document Rev Date Changes ChangeHistory Table of Contents Monaco Technical Reference Vii Viii List of Figures Table of Contents List of Tables Xii Features IntroductionProduct Operation Processors VME InterfacesPMC PEM Reference Documents General Bus Architecture On-Board Power Supply VME A24 Slave Interface Reset Reset ConditionsJtag Reset Sysreset Board Layout Board Layout Jumper settings Jumper Settings DescriptionOUT Part Number Processor Nodes Processor Configurations Populated Processor Node Block Diagram Processor Memory Configuration Internal MemoryExternal Memory 0x0180 DSP Memory Map Nodes B, C, and D Address Synchronous Dram Synchronous Burst SramProcessor Expansion Module Host Port Processor Boot Source Jumpers Node Processor Booting Serial Port Routing Serial Port Routing VME and PMC Connections for Serial Port PEM Connections for Serial Port 0 Global Shared Bus Global Shared Bus Access Source TargetMemory Arbitration Burst Cycle Bus Access Single Cycle Bus Access Locked Cycles Global Shared Bus VME64 Bus Interface VME OperationSCV64 Primary Slave A32/A24 Interface A24 Secondary Slave Interface Access A24 Secondary Interface Memory Map Hpia HPI Register Addresses VME address Master A32/A24/A16 SCV64 Interface VME64 Bus Interface DSP~LINK3 Data Transfer Operating Modes DSP~LINK3 Interface Astrben Address Strobe Control Mode DSP~LINK3 Reset Interface Signals DSP~LINK3 Interface Hurricane Configuration PCI InterfacePCI Offset Address Value Initialize Hurricane Register Set BCC2A PCI Device Hurricane Implementation Jtag Chain Jtag Debugging Jtag Debugging Overview Interrupt Handling Interrupt Routing DSP~LINK3 Interrupts to Node a PCI Bus Interrupts PEM InterruptsHurricane Interrupt SCV64 Interrupt KIPL2 KIPL1 KIPL0 Kipl Status Bits and the Iack Cycle Bit Node Whose Access Caused the Bus Error Bus Error Interrupts VME Host Interrupts To Any Node Inter-processor Interrupts Registers Register Address Summary Access Privilege Bus KFC2..0 KSIZE1..0 KADDR1..0 Vpage Register Vstatus Register Buserra KavecKIPL2..0 Vinta Register Vintb Register Vintc Register Vintd Register Kiplend Kipl Enable RegisterKiplenc Kiplenb DSP~LINK3 Register DL3RESET ID Register Hinta VME A24 Status RegisterHintb Hintc VME A24 Control Register Registers Board Identification SpecificationsMonaco Monaco67 General Specifications Parameter Performance and Data Throughput Data Access/Transfer Performance Specifications Connector Layout Connector Pinouts VME P1 Connector Pinout VME Connectors VME P2 Connector Pinout PMC to VME P2 VME P2 Connector DSP~LINK3 to VME P2 PMC Connector JN1 Pinout PMC Connectors PMC Connector JN2 PMC Connector JN4 Non-standard PMC Connector JN5 PEM 1 Connector Pinout PEM Connectors PEM 2 Connector Pinout Jtag Connectors Jtag in Connector PinoutJtag OUT Connector Connector Pinouts SCV64 Register Initialization Appendix a SCV64 Register Values SCV64 Register Initialization VME Index Interrupts to node A, 40 register Reset Jtag Sysreset