Spectrum Signal Processing Monaco Technical Reference
Global Shared Bus
Part Number 500-00191 19
Revision 2.00
3 Global Shared Bus
The Global Shared Bus provides access between devices on the Monaco board as shown
in the following table.
Table 8 Global Shared Bus Access
Source
Target ‘C6x
Nodes PMC
Site VME Bus

via SCV64

Internal program & data RAM R/W own node No Access No Access
Local SDRAM R/W own node No Access No Access
Local SBSRAM R/W own node No Access No Access
Global Shared RAM R/W (32-bit only) R/W R/W
Hurricane Registers R/W R/W R/W
PMC Site Hurricane DMA
access only - No Access
SCV64 Registers R/W No Access No Access
Global Shared Bus Registers R/W No Access No Access
VMEbus as master R/W No Access -

3.1. Memory

512K of 32-bit Asynchronous RAM, implemented in four 512K x 8-bit Asynchronous
RAM devices, is provided on the Global Shared Bus. The ‘C6x DSPs can only perform
32-bit accesses to the Global Shared RAM. Byte accesses are not supported.

3.2. Arbitration

Arbitration of the Global Shared Bus is implemented using a next bus owner token that is
passed serially from one device to the next. Token passing follows a strict hierarchical
sequence, ordered by bus servicing priority. There are six devices participating in the
process. These are, in decreasing priority:
• SCV64
• Hurricane
• DSP Node A
• DSP Node B
• DSP Node C
• DSP Node D