Spectrum Brands C6x VME64 VPAGE Register

Monaco Technical Reference Spectrum Signal Processing

Registers

46 Part Number 500-00191

Revision 2.00

VPAGE Register

Address: 016D 0000h

D31.. ..D24

Reserved

D23.. ..D20 D19 D18 D17 D16

Reserved KADDR31 KADDR30 KADDR29 KADDR28

D15 D14 D13 D12 D11 D10 D9 D8

KADDR27 KADDR26 KADDR25 KADDR24 KADDR23 KADDR22 KADDR21 KADDR20

D7 D6 D5 D4 D3 D2 D1 D0

Reserved KFC2 KFC1 KFC0 KSIZE1 KSIZE0 KADDR1 KADDR0

This register sets certain SCV64 address and control lines in order to extend the address

range of the ‘C6x processors and set up the type of VME cycle to be performed. Each

node has its own register. Except for D7 all other reserved bits are disconnected; D7 will

store what is written to it. These register is undefined upon reset and should be

initialized. Refer to the SCV64 User Manual for complete information on these signals.

KADDR[31..20]

Sets the upper 12 address bits that are latched to the SCV64 when the

‘C6x accesses the VME address space. This extends the 20 address bits

of the ‘C6x to the full 32 bits of the VME address space. This allows a

‘C6x access the entire VME bus as a master by setting these bits to

1 Mbyte region being accessed. A write to this register latches data lines

D19..8 and presents them to the SCV64 upper address lines

KADDR31..20 respectively. For example, a write to the VPAGE register

with data equal to 8 0000h causes the next outbound VME cycle (base

address 0170 0000h) with offset 0x0 to be addressed at VME address

8000 0000h.

KFC[2..0]

Sets the access type as User or Supervisor Program, or Data accesses.

Directly affects the address modifiers used for the VME Master cycle.

KSIZE[1..0]

Sets the number of bytes transferred for VME Master cycles. Directly

affects D32, D16, or D8 access type.

KADDR[1..0]

These bits allow the node, which is little endian in order to access the

PEM and PMCs, to access the SCV64, which is big endian.

Note:

Although access to VPAGE is local to each processor node, any read or

write to the register requires that the Global Shared Bus to be acquired. The

DSP’s cycles are extended until any current Global Shared Bus operations are

complete when accessing the VPAGE Register.

Contents

Main Page Preface Page Table of Contents vi Page Page List of Figures Page List of Tables Page 1 Introduction 1.1. Features Page 1.3. Reference Documents Introduction 4 1.4. General Bus Architecture Figure 1 Block Diagram The following block diagram shows the main components of the Monaco board. 1.5. On-Board Power Supply 1.6. Reset Conditions 1.6.1. VME SYSRESET 1.6.2. VME A24 Slave Interface Reset 1.6.3. JTAG Reset Introduction 1.7. Board Layout Figure 2 Board Layout The following diagram shows the board layout of the Monaco board. 1.8. Jumper settings Page 2 Processor Nodes 10 Figure 3 Processor Node Block Diagram 2.1. Processor Memory Configuration 2.1.1. Internal Memory 2.1.2. External Memory 12 Table 4 'C6x Internal Peripheral Register Values Register 0x0180 001C 0x0180 0018 0x0180 0014 Figure 4 DSP Memory Map Part Number 500-00191 13 14 Figure 5 DSP Memory Map for External-Memory Space CE1 2.2. Synchronous Burst SRAM 2.3. Synchronous DRAM 2.4. Processor Expansion Module 2.5. Host Port 2.6. Interrupt Lines 2.7. Processor Booting Part Number 500-00191 17 2.8. Serial Port Routing Figure 6 Serial Port Routing Node D Node C Node B 18 Table 7 VME and PMC Connections for Serial Port 1 3 Global Shared Bus via SCV64 3.1. Memory 3.2. Arbitration 3.2.1. Single Cycle Bus Access 3.2.2. Burst Cycle Bus Access 3.2.3. Locked Cycles Page 4 VME64 Bus Interface 4.1. VME Operation 4.2. SCV64 Primary Slave A32/A24 Interface 4.3. A24 Secondary Slave Interface VME64 Bus Interface all addresses mapped to 00 2008h all addresses mapped to 00 5008h all addresses mapped to 00 4008h all addresses mapped to 00 3008h Page 4.4. Master A32/A24/A16 SCV64 Interface Page 5 DSP~LINK3 Interface 5.1. DSP~LINK3 Data Transfer Operating Modes 5.2. Address Strobe Control Mode 5.3. Interface Signals 5.4. DSP~LINK3 Reset Page 6 PCI Interface 6.1. Hurricane Configuration PCI Interface 34 Table 11 Hurricane Register Set PCI Interface Part Number 500-00191 35 6.2. Hurricane Implementation 7 JTAG Debugging Page 8 Interrupt Handling 8.1. Overview Interrupt Handling 40 Figure 12 Interrupt Routing 8.2. DSP~LINK3 Interrupts to Node A 8.3. PEM Interrupts 8.4. PCI Bus Interrupts 8.5. Hurricane Interrupt 8.6. SCV64 Interrupt Page 8.7. Bus Error Interrupts 8.8. Inter-processor Interrupts 8.9. VME Host Interrupts To Any Node 9 Registers VPAGE Register VSTATUS Register Page VINTA Register VINTB Register VINTC Register VINTD Register KIPL Enable Register DSP~LINK3 Register ID Register VME A24 Status Register VME A24 Control Register Page 10 Specifications 10.1. Board Identification 10.2. General Specifications Part Number 500-00191 61 10.3. Performance and Data Throughput Page Part Number 500-00191 63 11 Connector Pinouts Node D Figure 13 Connector Layout Node C Node B 11.1. VME Connectors Part Number 500-00191 65 Table 17 VME P2 Connector Pinout (PMC to VME P2) 66 Table 18 VME P2 Connector (DSP~LINK3 to VME P2) Part Number 500-00191 67 11.2. PMC Connectors 68 Table 20 PMC Connector JN2 Part Number 500-00191 69 Table 21 PMC Connector JN4 70 Table 22 Non-standard PMC Connector JN5 Part Number 500-00191 71 11.3. PEM Connectors 72 Table 24 PEM 2 Connector Pinout Part Number 500-00191 73 11.4. JTAG Connectors Both JTAG connectors use 2 x 7, 0.1 x 0.1 bare pin headers. Table 25 JTAG IN Connector Pinout Table 26 JTAG OUT Connector Page SCV64 Register Values Part Number 500-00191 75 Appendix A: SCV64 Register Values SCV64 Register Values 76 Table 27 SCV64 Register Initialization Index A B C D E F G H I K L M P R T V