Processor Node Block Diagram | Spectrum Brands C6x VME64 specification

Monaco Technical Reference

Spectrum Signal Processing

Processor Nodes

		JTAG Test Bus
		‘C6x Host Port
		Interface (HPI) Bus
	Node Local
	Resources
		Serial
	‘C6x	Port 0
	DSP	Serial
		Serial
		Port 1
		128K x 32
		SBSRAM
	PEM Site
		4M x 32
	Shared with	SDRAM
	Node Pair
	DSP	DSP-LINK3
	Local	DSP-LINK3
	Local	Interface
	Bus	Interface
	Bus
		Node A
		Only
	Address Buffer
	and
	Data Latches

Global Shared Bus

Figure 3 Processor Node Block Diagram

10	Part Number 500-00191
	Revision 2.00

Image 22

Spectrum Brands C6x VME64 manual Processor Node Block Diagram

Contents

Monaco Revision Preface Iii Change Document Rev Date ChangesHistory Table of Contents Monaco Technical Reference Vii Viii List of Figures Table of Contents List of Tables Xii Introduction FeaturesProduct Operation Processors PMC InterfacesVME PEM Reference Documents On-Board Power Supply General Bus Architecture Jtag Reset Reset ConditionsVME A24 Slave Interface Reset Sysreset Board Layout Board Layout Jumper Settings Description Jumper settingsOUT Part Number Processor Configurations Populated Processor Nodes Processor Node Block Diagram Internal Memory Processor Memory ConfigurationExternal Memory 0x0180 DSP Memory Map Address Nodes B, C, and D Processor Expansion Module Synchronous Burst SramSynchronous Dram Host Port Processor Booting Processor Boot Source Jumpers Node Serial Port Routing Serial Port Routing PEM Connections for Serial Port 0 VME and PMC Connections for Serial Port Memory Global Shared Bus Access Source TargetGlobal Shared Bus Arbitration Single Cycle Bus Access Burst Cycle Bus Access Locked Cycles Global Shared Bus VME Operation VME64 Bus InterfaceSCV64 Primary Slave A32/A24 Interface Access A24 Secondary Slave Interface A24 Secondary Interface Memory Map HPI Register Addresses VME address Hpia Master A32/A24/A16 SCV64 Interface VME64 Bus Interface DSP~LINK3 Interface DSP~LINK3 Data Transfer Operating Modes Address Strobe Control Mode Astrben Interface Signals DSP~LINK3 Reset DSP~LINK3 Interface PCI Interface Hurricane ConfigurationPCI Offset Address Hurricane Register Set Value Initialize BCC2A Hurricane Implementation PCI Device Jtag Debugging Jtag Chain Jtag Debugging Interrupt Handling Overview DSP~LINK3 Interrupts to Node a Interrupt Routing Hurricane Interrupt PEM InterruptsPCI Bus Interrupts SCV64 Interrupt Kipl Status Bits and the Iack Cycle KIPL2 KIPL1 KIPL0 Bus Error Interrupts Bit Node Whose Access Caused the Bus Error Inter-processor Interrupts VME Host Interrupts To Any Node Register Address Summary Access Privilege Bus Registers Vpage Register KFC2..0 KSIZE1..0 KADDR1..0 Vstatus Register Kavec BuserraKIPL2..0 Vinta Register Vintb Register Vintc Register Vintd Register Kiplenc Kipl Enable RegisterKiplend Kiplenb DL3RESET DSP~LINK3 Register ID Register Hintb VME A24 Status RegisterHinta Hintc VME A24 Control Register Registers Monaco SpecificationsBoard Identification Monaco67 Specifications Parameter General Data Access/Transfer Performance Performance and Data Throughput Specifications Connector Pinouts Connector Layout VME Connectors VME P1 Connector Pinout VME P2 Connector Pinout PMC to VME P2 VME P2 Connector DSP~LINK3 to VME P2 PMC Connectors PMC Connector JN1 Pinout PMC Connector JN2 PMC Connector JN4 Non-standard PMC Connector JN5 PEM Connectors PEM 1 Connector Pinout PEM 2 Connector Pinout Jtag in Connector Pinout Jtag ConnectorsJtag OUT Connector Connector Pinouts Appendix a SCV64 Register Values SCV64 Register Initialization SCV64 Register Initialization Index VME Interrupts to node A, 40 register Reset Jtag Sysreset