Monaco Technical Reference | Spectrum Signal Processing |
Processor Nodes
2.7.Processor Booting
The ‘C6x can boot from either the VME bus (via its Host Port Interface (HPI) port) or from an
Table 5 Processor Boot Source Jumpers
Jumper | Node | PEM Boot | HPI Boot |
JP2 | Node A | IN | OUT |
JP3 | Node B | IN | OUT |
JP4 | Node C | IN | OUT |
JP5 | Node D | IN | OUT |
The Monaco board uses the CE1 memory space of the ‘C6x memory map 1 for the boot space upon power up or reset. Immediately after booting, the ‘C6x cannot access the resources in its CE1 space such as the Hurricane registers, Global Shared SRAM, and SCV64 Registers. In order to access these CE1 resources, the ‘C6x must toggle the state of its Timer 0 pin (TOUT0). The state of this pin is controlled by the DataOut bit of the ‘C6x Timer 0 Control Register. Once TOUT has been toggled, the CE1 resources are available to the ‘C6x until the ‘C6x is reset.
16 | Part Number |
| Revision 2.00 |
