Processor Memory Configuration | Spectrum Brands C6x VME64 specs

Spectrum Signal Processing	Monaco Technical Reference
	Processor Nodes

2.1.Processor Memory Configuration

Each ‘C6X DSP processor implements a 4 Gigabyte (full 32-bit) address space. This address space is partitioned into internal memory space and external memory space. External memory space is accessed through four memory select lines (CE0, CE1, CE2 and CE3).

2.1.1.Internal Memory

Internal memory space is further separated into three distinct regions:

∙internal program RAM (64Kbytes)

∙internal peripheral registers (2 Mbytes)

∙internal data RAM (64 Kbytes)

These three regions define memory space which is implemented in the DSP processor.

2.1.2.External Memory

External memory is segmented into 4 regions:

∙external memory interface CE0 (16 Mbytes)

∙external memory interface CE1 (4 Mbytes)

∙external memory interface CE2 (16 Mbytes)

∙external memory interface CE3 (16 Mbytes)

External memory (CE0, CE1, CE2 and CE3) consists of node local memory resources which are accessed on the DSP Local Bus, but are external to the DSP processor. The type of memory in each of the four CE regions is determined by settings in the internal peripheral registers. All remaining memory in the 4 GB address space is reserved.

The internal peripheral registers for Monaco must be initialized to the values in the following table upon reset for the board to operate.

Part Number 500-00191	11
Revision 2.00

Image 23

Spectrum Brands C6x VME64 manual Processor Memory Configuration, Internal Memory, External Memory

Contents

Monaco Revision Iii Preface History Document Rev Date ChangesChange Table of Contents Monaco Technical Reference Vii Viii List of Figures Table of Contents List of Tables Xii Product Operation Processors FeaturesIntroduction PEM InterfacesVME PMC Reference Documents General Bus Architecture On-Board Power Supply Sysreset Reset ConditionsVME A24 Slave Interface Reset Jtag Reset Board Layout Board Layout OUT Jumper settingsJumper Settings Description Part Number Processor Nodes Processor Configurations Populated Processor Node Block Diagram External Memory Processor Memory ConfigurationInternal Memory 0x0180 DSP Memory Map Nodes B, C, and D Address Host Port Synchronous Burst SramSynchronous Dram Processor Expansion Module Processor Boot Source Jumpers Node Processor Booting Serial Port Routing Serial Port Routing VME and PMC Connections for Serial Port PEM Connections for Serial Port 0 Arbitration Global Shared Bus Access Source TargetGlobal Shared Bus Memory Burst Cycle Bus Access Single Cycle Bus Access Locked Cycles Global Shared Bus SCV64 Primary Slave A32/A24 Interface VME64 Bus InterfaceVME Operation A24 Secondary Slave Interface Access A24 Secondary Interface Memory Map Hpia HPI Register Addresses VME address Master A32/A24/A16 SCV64 Interface VME64 Bus Interface DSP~LINK3 Data Transfer Operating Modes DSP~LINK3 Interface Astrben Address Strobe Control Mode DSP~LINK3 Reset Interface Signals DSP~LINK3 Interface PCI Offset Address Hurricane ConfigurationPCI Interface Value Initialize Hurricane Register Set BCC2A PCI Device Hurricane Implementation Jtag Chain Jtag Debugging Jtag Debugging Overview Interrupt Handling Interrupt Routing DSP~LINK3 Interrupts to Node a SCV64 Interrupt PEM InterruptsPCI Bus Interrupts Hurricane Interrupt KIPL2 KIPL1 KIPL0 Kipl Status Bits and the Iack Cycle Bit Node Whose Access Caused the Bus Error Bus Error Interrupts VME Host Interrupts To Any Node Inter-processor Interrupts Registers Register Address Summary Access Privilege Bus KFC2..0 KSIZE1..0 KADDR1..0 Vpage Register Vstatus Register KIPL2..0 BuserraKavec Vinta Register Vintb Register Vintc Register Vintd Register Kiplenb Kipl Enable RegisterKiplend Kiplenc DSP~LINK3 Register DL3RESET ID Register Hintc VME A24 Status RegisterHinta Hintb VME A24 Control Register Registers Monaco67 SpecificationsBoard Identification Monaco General Specifications Parameter Performance and Data Throughput Data Access/Transfer Performance Specifications Connector Layout Connector Pinouts VME P1 Connector Pinout VME Connectors VME P2 Connector Pinout PMC to VME P2 VME P2 Connector DSP~LINK3 to VME P2 PMC Connector JN1 Pinout PMC Connectors PMC Connector JN2 PMC Connector JN4 Non-standard PMC Connector JN5 PEM 1 Connector Pinout PEM Connectors PEM 2 Connector Pinout Jtag OUT Connector Jtag ConnectorsJtag in Connector Pinout Connector Pinouts SCV64 Register Initialization Appendix a SCV64 Register Values SCV64 Register Initialization VME Index Interrupts to node A, 40 register Reset Jtag Sysreset