Jtag Debugging, Jtag Chain | Spectrum Brands C6x VME64 guide

Spectrum Signal Processing	Monaco Technical Reference
	JTAG Debugging

7 JTAG Debugging

The Monaco board supports JTAG in-circuit emulation from a built in 74ACT8990 Test Bus Controller. The 74ACT8990 Test Bus Controller permits the VME interface to operate the JTAG chain. There are also two JTAG connectors for an XDS510 or White Mountain debugger, JTAG IN (J1) and JTAG OUT (J2), which can route the JTAG chain off-board.

JTAG in-circuit emulation is fed to the Test Bus Controller from the VME A24 secondary interface. C source debugging using an emulator board running a debug monitor on an adjacent computer is supported through the JTAG IN connector. If a JTAG IN connection with a clock signal is present the Test Bus Controller is automatically disconnected.

JTAG data lines are routed to each available ‘C6x node. The full JTAG chain is shown in the following diagram. Unpopulated processor nodes are bypassed.

TDO

TDO JTAG OUT

TDI

Routed back to JTAG IN if nothing is connected to

JTAG OUT

The Test Bus Controller		TDO
(TBC) is disabled		TDO
(TBC) is disabled
(bypassed) if an external				TDI
(bypassed) if an external		JTAG IN or TBC		TDI
debugger is connected to		JTAG IN or TBC
the JTAG IN connector.
the JTAG IN connector.

Node D ‘C6x

TDI

TDO

Node C ‘C6x

TDI

TDO

Node B ‘C6x

TDI

TDO

Node A ‘C6x

Figure 11 JTAG Chain

The JTAG IN input is buffered to reduce the load on an external JTAG device. The JTAG OUT output is buffered to guarantee enough drive to external JTAG loads. Up to three Monaco boards can be chained together through JTAG.

Part Number 500-00191	37
Revision 2.00

Image 49

Spectrum Brands C6x VME64 manual Jtag Debugging, Jtag Chain

Contents

Monaco Revision Iii Preface Change Document Rev Date ChangesHistory Table of Contents Monaco Technical Reference Vii Viii List of Figures Table of Contents List of Tables Xii Introduction FeaturesProduct Operation Processors VME InterfacesPMC PEM Reference Documents General Bus Architecture On-Board Power Supply VME A24 Slave Interface Reset Reset ConditionsJtag Reset Sysreset Board Layout Board Layout Jumper Settings Description Jumper settingsOUT Part Number Processor Nodes Processor Configurations Populated Processor Node Block Diagram Internal Memory Processor Memory ConfigurationExternal Memory 0x0180 DSP Memory Map Nodes B, C, and D Address Synchronous Dram Synchronous Burst SramProcessor Expansion Module Host Port Processor Boot Source Jumpers Node Processor Booting Serial Port Routing Serial Port Routing VME and PMC Connections for Serial Port PEM Connections for Serial Port 0 Global Shared Bus Global Shared Bus Access Source TargetMemory Arbitration Burst Cycle Bus Access Single Cycle Bus Access Locked Cycles Global Shared Bus VME Operation VME64 Bus InterfaceSCV64 Primary Slave A32/A24 Interface A24 Secondary Slave Interface Access A24 Secondary Interface Memory Map Hpia HPI Register Addresses VME address Master A32/A24/A16 SCV64 Interface VME64 Bus Interface DSP~LINK3 Data Transfer Operating Modes DSP~LINK3 Interface Astrben Address Strobe Control Mode DSP~LINK3 Reset Interface Signals DSP~LINK3 Interface PCI Interface Hurricane ConfigurationPCI Offset Address Value Initialize Hurricane Register Set BCC2A PCI Device Hurricane Implementation Jtag Chain Jtag Debugging Jtag Debugging Overview Interrupt Handling Interrupt Routing DSP~LINK3 Interrupts to Node a PCI Bus Interrupts PEM InterruptsHurricane Interrupt SCV64 Interrupt KIPL2 KIPL1 KIPL0 Kipl Status Bits and the Iack Cycle Bit Node Whose Access Caused the Bus Error Bus Error Interrupts VME Host Interrupts To Any Node Inter-processor Interrupts Registers Register Address Summary Access Privilege Bus KFC2..0 KSIZE1..0 KADDR1..0 Vpage Register Vstatus Register Kavec BuserraKIPL2..0 Vinta Register Vintb Register Vintc Register Vintd Register Kiplend Kipl Enable RegisterKiplenc Kiplenb DSP~LINK3 Register DL3RESET ID Register Hinta VME A24 Status RegisterHintb Hintc VME A24 Control Register Registers Board Identification SpecificationsMonaco Monaco67 General Specifications Parameter Performance and Data Throughput Data Access/Transfer Performance Specifications Connector Layout Connector Pinouts VME P1 Connector Pinout VME Connectors VME P2 Connector Pinout PMC to VME P2 VME P2 Connector DSP~LINK3 to VME P2 PMC Connector JN1 Pinout PMC Connectors PMC Connector JN2 PMC Connector JN4 Non-standard PMC Connector JN5 PEM 1 Connector Pinout PEM Connectors PEM 2 Connector Pinout Jtag in Connector Pinout Jtag ConnectorsJtag OUT Connector Connector Pinouts SCV64 Register Initialization Appendix a SCV64 Register Values SCV64 Register Initialization VME Index Interrupts to node A, 40 register Reset Jtag Sysreset