Board Layout | Spectrum Brands C6x VME64 specs

Monaco Technical Reference

Spectrum Signal Processing

Introduction

1.7.Board Layout

The following diagram shows the board layout of the Monaco board.

JP10 JP9 JP8 JP7			JP4 JP5
JN6	JN7		Node D
JN6	JN7		‘C6x
			‘C6x
		PEM Site
		Nodes C and D			VME
					VME
JN8	JN9		Node C		P1
JN8	JN9		Node C
			‘C6x
JN10	JN11		Node B
			Node B	JP3
			‘C6x	JP3
		PEM Site		JP2
		Nodes A and B		JP1
		Nodes A and B		1	2
				1	2
				3	4
JN12	JN13			5	6
JN12	JN13			7	8
			Node A	7	8
				8	9
				10 11
			‘C6x	10 11
			‘C6x	12 13
			JN1	JN2
			JN5
					VME
		PMC Site			P2
		PMC Site
				JN4
		J3
J1		J2
JTAG IN		JTAG OUT	J8
Connector		Connector	DSP~LINK3 Ribbon Cable Connector

Figure 2 Board Layout

6	Part Number 500-00191

Revision 2.00

Image 18

Spectrum Brands C6x VME64 manual Board Layout

Contents

Monaco Revision Preface Iii Document Rev Date Changes ChangeHistory Table of Contents Monaco Technical Reference Vii Viii List of Figures Table of Contents List of Tables Xii Features IntroductionProduct Operation Processors PMC InterfacesVME PEM Reference Documents On-Board Power Supply General Bus Architecture Jtag Reset Reset ConditionsVME A24 Slave Interface Reset Sysreset Board Layout Board Layout Jumper settings Jumper Settings DescriptionOUT Part Number Processor Configurations Populated Processor Nodes Processor Node Block Diagram Processor Memory Configuration Internal MemoryExternal Memory 0x0180 DSP Memory Map Address Nodes B, C, and D Processor Expansion Module Synchronous Burst SramSynchronous Dram Host Port Processor Booting Processor Boot Source Jumpers Node Serial Port Routing Serial Port Routing PEM Connections for Serial Port 0 VME and PMC Connections for Serial Port Memory Global Shared Bus Access Source TargetGlobal Shared Bus Arbitration Single Cycle Bus Access Burst Cycle Bus Access Locked Cycles Global Shared Bus VME64 Bus Interface VME OperationSCV64 Primary Slave A32/A24 Interface Access A24 Secondary Slave Interface A24 Secondary Interface Memory Map HPI Register Addresses VME address Hpia Master A32/A24/A16 SCV64 Interface VME64 Bus Interface DSP~LINK3 Interface DSP~LINK3 Data Transfer Operating Modes Address Strobe Control Mode Astrben Interface Signals DSP~LINK3 Reset DSP~LINK3 Interface Hurricane Configuration PCI InterfacePCI Offset Address Hurricane Register Set Value Initialize BCC2A Hurricane Implementation PCI Device Jtag Debugging Jtag Chain Jtag Debugging Interrupt Handling Overview DSP~LINK3 Interrupts to Node a Interrupt Routing Hurricane Interrupt PEM InterruptsPCI Bus Interrupts SCV64 Interrupt Kipl Status Bits and the Iack Cycle KIPL2 KIPL1 KIPL0 Bus Error Interrupts Bit Node Whose Access Caused the Bus Error Inter-processor Interrupts VME Host Interrupts To Any Node Register Address Summary Access Privilege Bus Registers Vpage Register KFC2..0 KSIZE1..0 KADDR1..0 Vstatus Register Buserra KavecKIPL2..0 Vinta Register Vintb Register Vintc Register Vintd Register Kiplenc Kipl Enable RegisterKiplend Kiplenb DL3RESET DSP~LINK3 Register ID Register Hintb VME A24 Status RegisterHinta Hintc VME A24 Control Register Registers Monaco SpecificationsBoard Identification Monaco67 Specifications Parameter General Data Access/Transfer Performance Performance and Data Throughput Specifications Connector Pinouts Connector Layout VME Connectors VME P1 Connector Pinout VME P2 Connector Pinout PMC to VME P2 VME P2 Connector DSP~LINK3 to VME P2 PMC Connectors PMC Connector JN1 Pinout PMC Connector JN2 PMC Connector JN4 Non-standard PMC Connector JN5 PEM Connectors PEM 1 Connector Pinout PEM 2 Connector Pinout Jtag Connectors Jtag in Connector PinoutJtag OUT Connector Connector Pinouts Appendix a SCV64 Register Values SCV64 Register Initialization SCV64 Register Initialization Index VME Interrupts to node A, 40 register Reset Jtag Sysreset