Address Strobe Control Mode, Astrben | Spectrum Brands C6x VME64

Monaco Technical Reference	Spectrum Signal Processing
DSP~LINK3 Interface

Table 10 DSP~LINK3 Data Transfer Operating Modes

	Base	ASTRB_EN
Mode	Address	Bit	Description

Standard	0160 0000h	x	For slave boards that are similar to DSP~LINK1
Access			slave boards and operate with a fixed access
			time.

Standard	0164 0000h	0	For DSP~LINK3 slave boards that have fast,
Fast			fixed access time. This memory space is
Access			shared with the Address Strobe Control
			operating mode.
Address	0164 0000h	1	For slave boards that require more than the
Strobe			16 KWords of addressing provided by the
Control			standard DSP~LINK3 address lines. The bus
			master uses the /ASTRB cycle to place the
			page address onto the DSP~LINK3 data lines.
			It determines which address page is accessed
			on the slave board. This allows access to up to
			214 address pages with each address page
			having an address depth of 214. The /ASTRB
			Cycle has the same timing as the Standard
			Fast transfer cycle.

Ready	0168 0000h	x	For DSP~LINK3 slave boards that require
Control			variable length access times. /DSTRB is active
Access			until the slave asserts the DSP~LINK3 ready
			signal (/RDY) to end the cycle.

5.2.Address Strobe Control Mode

The Address Strobe Control mode uses the same node A 64K address space as the Standard Fast Access mode. The Address Strobe Control mode is enabled for this space by setting bit D1, the ASTRB_EN bit, of the DSP~LINK3 register to “1”. This register is located at address 016D 8018h of node A. Standard Fast Access mode writes will now generate /ASTRB cycles. The DSP~LINK3 slave attached to the Monaco board should then latch the lower addresses.

30	Part Number 500-00191
	Revision 2.00

Image 42

Spectrum Brands C6x VME64 manual Address Strobe Control Mode, Astrben

Contents

Monaco Revision Preface Iii Document Rev Date Changes ChangeHistory Table of Contents Monaco Technical Reference Vii Viii List of Figures Table of Contents List of Tables Xii Features IntroductionProduct Operation Processors PMC InterfacesVME PEM Reference Documents On-Board Power Supply General Bus Architecture Jtag Reset Reset ConditionsVME A24 Slave Interface Reset Sysreset Board Layout Board Layout Jumper settings Jumper Settings DescriptionOUT Part Number Processor Configurations Populated Processor Nodes Processor Node Block Diagram Processor Memory Configuration Internal MemoryExternal Memory 0x0180 DSP Memory Map Address Nodes B, C, and D Processor Expansion Module Synchronous Burst SramSynchronous Dram Host Port Processor Booting Processor Boot Source Jumpers Node Serial Port Routing Serial Port Routing PEM Connections for Serial Port 0 VME and PMC Connections for Serial Port Memory Global Shared Bus Access Source TargetGlobal Shared Bus Arbitration Single Cycle Bus Access Burst Cycle Bus Access Locked Cycles Global Shared Bus VME64 Bus Interface VME OperationSCV64 Primary Slave A32/A24 Interface Access A24 Secondary Slave Interface A24 Secondary Interface Memory Map HPI Register Addresses VME address Hpia Master A32/A24/A16 SCV64 Interface VME64 Bus Interface DSP~LINK3 Interface DSP~LINK3 Data Transfer Operating Modes Address Strobe Control Mode Astrben Interface Signals DSP~LINK3 Reset DSP~LINK3 Interface Hurricane Configuration PCI InterfacePCI Offset Address Hurricane Register Set Value Initialize BCC2A Hurricane Implementation PCI Device Jtag Debugging Jtag Chain Jtag Debugging Interrupt Handling Overview DSP~LINK3 Interrupts to Node a Interrupt Routing Hurricane Interrupt PEM InterruptsPCI Bus Interrupts SCV64 Interrupt Kipl Status Bits and the Iack Cycle KIPL2 KIPL1 KIPL0 Bus Error Interrupts Bit Node Whose Access Caused the Bus Error Inter-processor Interrupts VME Host Interrupts To Any Node Register Address Summary Access Privilege Bus Registers Vpage Register KFC2..0 KSIZE1..0 KADDR1..0 Vstatus Register Buserra KavecKIPL2..0 Vinta Register Vintb Register Vintc Register Vintd Register Kiplenc Kipl Enable RegisterKiplend Kiplenb DL3RESET DSP~LINK3 Register ID Register Hintb VME A24 Status RegisterHinta Hintc VME A24 Control Register Registers Monaco SpecificationsBoard Identification Monaco67 Specifications Parameter General Data Access/Transfer Performance Performance and Data Throughput Specifications Connector Pinouts Connector Layout VME Connectors VME P1 Connector Pinout VME P2 Connector Pinout PMC to VME P2 VME P2 Connector DSP~LINK3 to VME P2 PMC Connectors PMC Connector JN1 Pinout PMC Connector JN2 PMC Connector JN4 Non-standard PMC Connector JN5 PEM Connectors PEM 1 Connector Pinout PEM 2 Connector Pinout Jtag Connectors Jtag in Connector PinoutJtag OUT Connector Connector Pinouts Appendix a SCV64 Register Values SCV64 Register Initialization SCV64 Register Initialization Index VME Interrupts to node A, 40 register Reset Jtag Sysreset