Interrupts to node A, 40 register Reset | Spectrum Brands C6x VME64

Monaco Technical Reference

Index

interrupts to node A, 40 register, 54

reset, 31

assert or release, 54

standard fast accesses, control, 54

E

EEPROM, 16 enable interrupt

from SCV64 to a node, 53 external memory space of DSP, 11

F

features of the board, 1 fixed-point, 1 floating-point, 1

G

generate interrupt to node A, 49 to node B, 50 to node C, 51 to node D, 52

global shared bus, 19 access

burst cycle, 20 locked cycle, 21 locking, 21

precautions to follow, 21 single cycle, 20

arbitration, 19 memory, 19

H

handling interrupts, 39 Host Port Interface, 15, 26

register addresses, 26 HPI. See Host Port Interface Hurricane, 33

configuring, 33 implementation, 36 interrupts, 41 register set, 34

I

ID register, 55

78

Spectrum Signal Processing

identifying processor the software is running on, 55

IDSEL line, 36 INT4 interrupt

identify source, 47 interface

DSP~LINK3, 29 PCI, 33 signals

DSP~LINK3, 31

internal memory space of DSP, 11 internal peripheral register values, C6x,

12

inter-processor interrupts, 44 interrupt

bus error, 43 DSP~LINK3

to node A, 40

enable

from SCV64 to a node, 53

handling, 39 Hurricane, 41 INT4

identify source, 47

inter-processor, 44 lines, 15

node A, to, 49 node B, to, 50 node C, to, 51 node D, to, 52 PCI, 41 PEM, 41 routing, 40 SCV64, 41

enable to a node, 53

VME host to any node, 44

J

JN1 connector, 67 JN2 connector, 68 JN4 connector, 69 JN5 connector, 70 JTAG, 2

connector, 73

IN, 73

OUT, 73

debugging, 37 reset, 5

JTAG chain, 37

JTAG IN connector, 73

Part Number 500-00191

Revision 2.00

Image 90

Spectrum Brands C6x VME64 manual Interrupts to node A, 40 register Reset

Contents

Monaco Revision Preface Iii Document Rev Date Changes ChangeHistory Table of Contents Monaco Technical Reference Vii Viii List of Figures Table of Contents List of Tables Xii Features IntroductionProduct Operation Processors PMC InterfacesVME PEM Reference Documents On-Board Power Supply General Bus Architecture Jtag Reset Reset ConditionsVME A24 Slave Interface Reset Sysreset Board Layout Board Layout Jumper settings Jumper Settings DescriptionOUT Part Number Processor Configurations Populated Processor Nodes Processor Node Block Diagram Processor Memory Configuration Internal MemoryExternal Memory 0x0180 DSP Memory Map Address Nodes B, C, and D Processor Expansion Module Synchronous Burst SramSynchronous Dram Host Port Processor Booting Processor Boot Source Jumpers Node Serial Port Routing Serial Port Routing PEM Connections for Serial Port 0 VME and PMC Connections for Serial Port Memory Global Shared Bus Access Source TargetGlobal Shared Bus Arbitration Single Cycle Bus Access Burst Cycle Bus Access Locked Cycles Global Shared Bus VME64 Bus Interface VME OperationSCV64 Primary Slave A32/A24 Interface Access A24 Secondary Slave Interface A24 Secondary Interface Memory Map HPI Register Addresses VME address Hpia Master A32/A24/A16 SCV64 Interface VME64 Bus Interface DSP~LINK3 Interface DSP~LINK3 Data Transfer Operating Modes Address Strobe Control Mode Astrben Interface Signals DSP~LINK3 Reset DSP~LINK3 Interface Hurricane Configuration PCI InterfacePCI Offset Address Hurricane Register Set Value Initialize BCC2A Hurricane Implementation PCI Device Jtag Debugging Jtag Chain Jtag Debugging Interrupt Handling Overview DSP~LINK3 Interrupts to Node a Interrupt Routing Hurricane Interrupt PEM InterruptsPCI Bus Interrupts SCV64 Interrupt Kipl Status Bits and the Iack Cycle KIPL2 KIPL1 KIPL0 Bus Error Interrupts Bit Node Whose Access Caused the Bus Error Inter-processor Interrupts VME Host Interrupts To Any Node Register Address Summary Access Privilege Bus Registers Vpage Register KFC2..0 KSIZE1..0 KADDR1..0 Vstatus Register Buserra KavecKIPL2..0 Vinta Register Vintb Register Vintc Register Vintd Register Kiplenc Kipl Enable RegisterKiplend Kiplenb DL3RESET DSP~LINK3 Register ID Register Hintb VME A24 Status RegisterHinta Hintc VME A24 Control Register Registers Monaco SpecificationsBoard Identification Monaco67 Specifications Parameter General Data Access/Transfer Performance Performance and Data Throughput Specifications Connector Pinouts Connector Layout VME Connectors VME P1 Connector Pinout VME P2 Connector Pinout PMC to VME P2 VME P2 Connector DSP~LINK3 to VME P2 PMC Connectors PMC Connector JN1 Pinout PMC Connector JN2 PMC Connector JN4 Non-standard PMC Connector JN5 PEM Connectors PEM 1 Connector Pinout PEM 2 Connector Pinout Jtag Connectors Jtag in Connector PinoutJtag OUT Connector Connector Pinouts Appendix a SCV64 Register Values SCV64 Register Initialization SCV64 Register Initialization Index VME Interrupts to node A, 40 register Reset Jtag Sysreset