Spectrum Signal Processing Monaco Technical Reference
SCV64 Register Values
Part Number 500-00191 79
Revision 2.00
JTAG OUT connector, 73
jumper settings, 7
setting DSP boot source, 16
K
KIPL
enable register, 53
status bits, 42
L
locked cycle (global shared bus access),
21
locking
global shared bus, 21
precautions to follow, 21
M
memory
configuration, DSP, 11
global shared bus, 19
map
DSP, 13
external-memory space CE1, 14
PCI, 33
primary VME A24/A32, 24
secondary VME A24, 25
Monaco67, 1
P
P1 connector, 64
P2 connector, 65
PCI
IDSEL line of device, 36
interface, 33
interrupts, 41
memory map, 33
PEM, 2, 15
connector, 71
PEM 1, 71
PEM 2, 72
interrupts, 41
performance specifications, 61
pinout. See connector
PMC, 2
connector, 67
JN1, 67
JN2, 68
JN4, 69
JN5, 70
power supply, 4
processor. See DSP
Processor Expansion Module. See PEM
R
reference documents, 3
register, 45
address summary, 45
C6x internal peripheral, 12
DSP~LINK3, 54
Host Port Interface
addresses, 26
Hurricane register set, 34
ID, 55
KIPL enable, 53
SCV64 VME64, 75
VINTA, 49
VINTB, 50
VINTC, 51
VINTD, 52
VME A24 control register, 57
VME A24 status register, 56
VPAGE, 27, 46
VSTATUS, 27, 47
reset, 5
DSP~LINK3, 31
assert or release, 54
JTAG, 5
VME A24 slave interface reset, 5
VME SYSRESET, 5
routing
interrupts, 40
serial ports, 17
S
SBSRAM, 15
SCV64 VME64 interface
interrupts, 41
master, 27
memory map
primary, 24
secondary interface, 25
primary slave, 23
register initialization, 75
secondary slave, 24
VPAGE register, 46
SDRAM, 15
serial ports, 2
pin assignments, 18