Monaco Technical Reference Spectrum Signal Processing
VME64 Bus Interface
24 Part Number 500-00191
Revision 2.00
VME Offset Address Access
0000 0000h
Host
Global Shared SRAM
(lower 1Mbyte)
VME DSP
000F FFFFh
accessible and
0010 0000h
Hurricane
Global Shared SRAM
(Upper 1 Mbyte)
accessible
001F FFFFh
0020 0000h
Hurricane Control Registers
002F FFFFh
0030 0000h
Reserved
003F FFFFh
Figure 8 Primary VME A24/A32 Memory Map
Note:
The full A24 memory map occupies one-quarter of the available A24
space. This can be reduced to the standard 512K (16M ÷ 32) of the available
A24 space by mapping only the lower 512 Kbytes (128k x 32) of the global
shared SRAM. This is entirely programmable in the SCV64 base address
registers. Only SCV64 A21 and A20 are used for decode on SCV64 VME slave
accesses to the board. D16 and D08E0 writes are not supported on the primary
A32/A24 interface.
4.3. A24 Secondary Slave Interface
Jumper block JP1 sets address bits A23..A17 of the VME A24 slave interface. This base
address defines a 128K byte addressed memory space accessed by the VME bus. Access
to this space from the VME bus bypasses the SCV64 VME bus interface chip.
All A24 VME transfer types are accepted except for LOCK, and MBLT types.
As shown in the following memory map, the A24 slave interface provides the VME bus
direct access to:
• The Host Port Interface (HPI) registers of each ‘C6x processor
• The Test Bus Controller (TBC) for JTAG debugging operation
• Control and Status registers of the Monaco board
D16 and D08E0 accesses are not supported on the slave A24 secondary interface.