Spectrum Brands C6x VME64 3.2.3. Locked Cycles

Spectrum Signal Processing Monaco Technical Reference

Global Shared Bus

Part Number 500-00191 21

Revision 2.00

Although this is a non-prioritized scheme, the back-off function of the SCV64 interface

resolves collisions between a bus master and the VMEbus if there is contention for the

VMEbus.

Note:

There are no ownership timers for the Hurricane or SCV64. If the

Hurricane holds the bus too long the VME bus could timeout.

3.2.3. Locked Cycles

A ‘C6x can lock the Global Shared Bus in order to perform Read-Modify-Write (RMW)

or other atomic accesses to it, by driving its Timer 0 (TOUT0) low. After the TOUT0 is

driven low, the next access to the Global Shared Bus acquires the bus. The bus is not

released until the ‘C6x drives the Timer 0 (TOUT0) pin high.

Caution:

The capability of locking the Global Shared Bus from a ‘C6x should

be used carefully because other devices will not acquire the bus once it is locked.

This capability is intended for read-modify-write accesses to the Global Shared

RAM and registers. It is highly recommended that Bus locking not be used. It

can lead to a deadlock condition, and in particular, result in debugger timeouts.

The following precautions should be observed when locking the Global Shared Bus:

1. VME bus timeouts can occur because the SCV64 cannot access the board while a

‘C6x has locked the bus.

2. If node A accesses the DSP~LINK3 interface while it has locked the Global Shared

Bus by asserting TOUT0, the bus will be released. Node A’s next access to the bus

will re-lock it to node A, providing that TOUT0 is still asserted.

3. Some SCV64 inbound cycles can occur while the bus is locked. If a ‘C6x has locked

the bus and is performing a VME outbound cycle while a VME inbound cycle is in

progress, the ‘C6x will be temporarily backed off and the SCV64 cycle will proceed.

The Global Shared Bus will be returned to that ‘C6x node after the SCV64 cycle

finishes. No other ‘C6x will get ownership of the bus.

4. If a debugger is being used when one processor has the bus locked for an extended

time while another processor is trying to get the bus, the debugger may timeout.

Contents

Main Page Preface Page Table of Contents vi Page Page List of Figures Page List of Tables Page 1 Introduction 1.1. Features Page 1.3. Reference Documents Introduction 4 1.4. General Bus Architecture Figure 1 Block Diagram The following block diagram shows the main components of the Monaco board. 1.5. On-Board Power Supply 1.6. Reset Conditions 1.6.1. VME SYSRESET 1.6.2. VME A24 Slave Interface Reset 1.6.3. JTAG Reset Introduction 1.7. Board Layout Figure 2 Board Layout The following diagram shows the board layout of the Monaco board. 1.8. Jumper settings Page 2 Processor Nodes 10 Figure 3 Processor Node Block Diagram 2.1. Processor Memory Configuration 2.1.1. Internal Memory 2.1.2. External Memory 12 Table 4 'C6x Internal Peripheral Register Values Register 0x0180 001C 0x0180 0018 0x0180 0014 Figure 4 DSP Memory Map Part Number 500-00191 13 14 Figure 5 DSP Memory Map for External-Memory Space CE1 2.2. Synchronous Burst SRAM 2.3. Synchronous DRAM 2.4. Processor Expansion Module 2.5. Host Port 2.6. Interrupt Lines 2.7. Processor Booting Part Number 500-00191 17 2.8. Serial Port Routing Figure 6 Serial Port Routing Node D Node C Node B 18 Table 7 VME and PMC Connections for Serial Port 1 3 Global Shared Bus via SCV64 3.1. Memory 3.2. Arbitration 3.2.1. Single Cycle Bus Access 3.2.2. Burst Cycle Bus Access 3.2.3. Locked Cycles Page 4 VME64 Bus Interface 4.1. VME Operation 4.2. SCV64 Primary Slave A32/A24 Interface 4.3. A24 Secondary Slave Interface VME64 Bus Interface all addresses mapped to 00 2008h all addresses mapped to 00 5008h all addresses mapped to 00 4008h all addresses mapped to 00 3008h Page 4.4. Master A32/A24/A16 SCV64 Interface Page 5 DSP~LINK3 Interface 5.1. DSP~LINK3 Data Transfer Operating Modes 5.2. Address Strobe Control Mode 5.3. Interface Signals 5.4. DSP~LINK3 Reset Page 6 PCI Interface 6.1. Hurricane Configuration PCI Interface 34 Table 11 Hurricane Register Set PCI Interface Part Number 500-00191 35 6.2. Hurricane Implementation 7 JTAG Debugging Page 8 Interrupt Handling 8.1. Overview Interrupt Handling 40 Figure 12 Interrupt Routing 8.2. DSP~LINK3 Interrupts to Node A 8.3. PEM Interrupts 8.4. PCI Bus Interrupts 8.5. Hurricane Interrupt 8.6. SCV64 Interrupt Page 8.7. Bus Error Interrupts 8.8. Inter-processor Interrupts 8.9. VME Host Interrupts To Any Node 9 Registers VPAGE Register VSTATUS Register Page VINTA Register VINTB Register VINTC Register VINTD Register KIPL Enable Register DSP~LINK3 Register ID Register VME A24 Status Register VME A24 Control Register Page 10 Specifications 10.1. Board Identification 10.2. General Specifications Part Number 500-00191 61 10.3. Performance and Data Throughput Page Part Number 500-00191 63 11 Connector Pinouts Node D Figure 13 Connector Layout Node C Node B 11.1. VME Connectors Part Number 500-00191 65 Table 17 VME P2 Connector Pinout (PMC to VME P2) 66 Table 18 VME P2 Connector (DSP~LINK3 to VME P2) Part Number 500-00191 67 11.2. PMC Connectors 68 Table 20 PMC Connector JN2 Part Number 500-00191 69 Table 21 PMC Connector JN4 70 Table 22 Non-standard PMC Connector JN5 Part Number 500-00191 71 11.3. PEM Connectors 72 Table 24 PEM 2 Connector Pinout Part Number 500-00191 73 11.4. JTAG Connectors Both JTAG connectors use 2 x 7, 0.1 x 0.1 bare pin headers. Table 25 JTAG IN Connector Pinout Table 26 JTAG OUT Connector Page SCV64 Register Values Part Number 500-00191 75 Appendix A: SCV64 Register Values SCV64 Register Values 76 Table 27 SCV64 Register Initialization Index A B C D E F G H I K L M P R T V