DSP~LINK3 Interrupts to Node a | Spectrum Brands C6x VME64 specification

Monaco Technical Reference

Spectrum Signal Processing

Interrupt Handling

KIPL D Enable

SCV64 Interrupt

VME Interrupt

BUSERR_D

INT 4

VINTD

PCI Interrupt

INT 5

Node D

'C6x

PEM INT1

INT 6

PEM INT2

Hurricane

INT 7

KIPL C Enable

VME Interrupt

INT 4

BUSERR_C

VINTC

PCI Interrupt

INT 5

Node C

'C6x

PEM INT1

INT 6

PEM INT2

Hurricane

INT 7

KIPL B Enable

VME Interrupt

INT 4

BUSERR_B

VINTB

PCI Interrupt

INT 5

Node B

'C6x

PEM INT1

INT 6

PEM INT2

Hurricane

INT 7

KIPL A Enable

VME Interrupt

BUSERR_A

INT 4

PCI Interrupt

VINTA

INT 5

Node A

Hurricane

Hurricane

'C6x

PEM INT1

INT 6

PCI Bus

INTA

De-Bounce Logic

PEM INT2

INTB

INT 7

Interrupts

INTC

INTD

DSP~LINK3

INT0

Note

INT1

‘C6x interrupts

Interface

De-Bounce Logic

are rising edge-

INT2

Interrupts

triggered.

INT3

Figure 12 Interrupt Routing

8.2.DSP~LINK3 Interrupts to Node A

The four active-low interrupts from the DSP~LINK3 interface are logically OR’ed and routed to the INT7 interrupt input of the node A ‘C6x. The open-collector signals are de- bounced. The interrupts are not latched on the Monaco board and must be cleared on the DSP~LINK3 board that generated them.

40	Part Number 500-00191
	Revision 2.00

Image 52

Spectrum Brands C6x VME64 manual DSP~LINK3 Interrupts to Node a, Interrupt Routing

Contents

Monaco Revision Preface Iii Change Document Rev Date ChangesHistory Table of Contents Monaco Technical Reference Vii Viii List of Figures Table of Contents List of Tables Xii Introduction FeaturesProduct Operation Processors Interfaces VMEPMC PEM Reference Documents On-Board Power Supply General Bus Architecture Reset Conditions VME A24 Slave Interface ResetJtag Reset Sysreset Board Layout Board Layout Jumper Settings Description Jumper settingsOUT Part Number Processor Configurations Populated Processor Nodes Processor Node Block Diagram Internal Memory Processor Memory ConfigurationExternal Memory 0x0180 DSP Memory Map Address Nodes B, C, and D Synchronous Burst Sram Synchronous DramProcessor Expansion Module Host Port Processor Booting Processor Boot Source Jumpers Node Serial Port Routing Serial Port Routing PEM Connections for Serial Port 0 VME and PMC Connections for Serial Port Global Shared Bus Access Source Target Global Shared BusMemory Arbitration Single Cycle Bus Access Burst Cycle Bus Access Locked Cycles Global Shared Bus VME Operation VME64 Bus InterfaceSCV64 Primary Slave A32/A24 Interface Access A24 Secondary Slave Interface A24 Secondary Interface Memory Map HPI Register Addresses VME address Hpia Master A32/A24/A16 SCV64 Interface VME64 Bus Interface DSP~LINK3 Interface DSP~LINK3 Data Transfer Operating Modes Address Strobe Control Mode Astrben Interface Signals DSP~LINK3 Reset DSP~LINK3 Interface PCI Interface Hurricane ConfigurationPCI Offset Address Hurricane Register Set Value Initialize BCC2A Hurricane Implementation PCI Device Jtag Debugging Jtag Chain Jtag Debugging Interrupt Handling Overview DSP~LINK3 Interrupts to Node a Interrupt Routing PEM Interrupts PCI Bus InterruptsHurricane Interrupt SCV64 Interrupt Kipl Status Bits and the Iack Cycle KIPL2 KIPL1 KIPL0 Bus Error Interrupts Bit Node Whose Access Caused the Bus Error Inter-processor Interrupts VME Host Interrupts To Any Node Register Address Summary Access Privilege Bus Registers Vpage Register KFC2..0 KSIZE1..0 KADDR1..0 Vstatus Register Kavec BuserraKIPL2..0 Vinta Register Vintb Register Vintc Register Vintd Register Kipl Enable Register KiplendKiplenc Kiplenb DL3RESET DSP~LINK3 Register ID Register VME A24 Status Register HintaHintb Hintc VME A24 Control Register Registers Specifications Board IdentificationMonaco Monaco67 Specifications Parameter General Data Access/Transfer Performance Performance and Data Throughput Specifications Connector Pinouts Connector Layout VME Connectors VME P1 Connector Pinout VME P2 Connector Pinout PMC to VME P2 VME P2 Connector DSP~LINK3 to VME P2 PMC Connectors PMC Connector JN1 Pinout PMC Connector JN2 PMC Connector JN4 Non-standard PMC Connector JN5 PEM Connectors PEM 1 Connector Pinout PEM 2 Connector Pinout Jtag in Connector Pinout Jtag ConnectorsJtag OUT Connector Connector Pinouts Appendix a SCV64 Register Values SCV64 Register Initialization SCV64 Register Initialization Index VME Interrupts to node A, 40 register Reset Jtag Sysreset