Spectrum Brands C6x VME64 - page 54

Monaco Technical Reference Spectrum Signal Processing

Interrupt Handling

42 Part Number 500-00191

Revision 2.00

The /KIPL[2..0] status bits, D[2..0], in the VSTATUS Register indicate the priority

level of the SCV64 interrupt. These bits reflect the state of the /KIPL lines from the

SCV64. If all three active-low bits are set to “1” (inactive), then an SCV64 interrupt did

not cause the INT4 interrupt.

If the interrupt was due to an SCV64 interrupt, it is serviced by performing an IACK

cycle to the SCV64. An IACK cycle is a special type of VME read cycle to a specific

location in the IACK cycle space (base address 016F 0000h).

For an IACK read cycle, bits D[0..7] of the VPAGE Register must be initialized in the

following way:

• KADDR0 (bit D0) is set to “0”

• The value of the /KIPL0 bit in the VSTATUS Register is inverted and placed in

the KADDR1 bit (bit D1)

• KSIZE0 (bit D2) is set to “1”

• KSIZE1 (bit D3) is set to “0”

• All three KFC bits (bits D[6..4]) are set to “1”

The /KIPL[2..1] status bits, D[2..1], in the VSTATUS Register determine the offset of

the address to read within the IACK cycle space.

• /KIPL2 is inverted to determine IACK address bit A3

• /KIPL1 is inverted to determine IACK address bit A2

The following table summarizes how the /KIPL[2..1] bits in the VSTATUS Register

initialize the VPAGE Register and set the IACK cycle address.

Table 12 KIPL Status Bits and the IACK Cycle

/KIPL2 /KIPL1 /KIPL0 VPAGE KADDR1 IACK Address

1 1 1 Not Used Not Used

1 1 0 1 016F 0000h

1 0 1 0 016F 0004h

1 0 0 1 016F 0004h

0 1 1 0 016F 0008h

0 1 0 1 016F 0008h

0 0 1 0 016F 000Ch

0 0 0 1 016F 000Ch

Contents

Main Page Preface Page Table of Contents vi Page Page List of Figures Page List of Tables Page 1 Introduction 1.1. Features Page 1.3. Reference Documents Introduction 4 1.4. General Bus Architecture Figure 1 Block Diagram The following block diagram shows the main components of the Monaco board. 1.5. On-Board Power Supply 1.6. Reset Conditions 1.6.1. VME SYSRESET 1.6.2. VME A24 Slave Interface Reset 1.6.3. JTAG Reset Introduction 1.7. Board Layout Figure 2 Board Layout The following diagram shows the board layout of the Monaco board. 1.8. Jumper settings Page 2 Processor Nodes 10 Figure 3 Processor Node Block Diagram 2.1. Processor Memory Configuration 2.1.1. Internal Memory 2.1.2. External Memory 12 Table 4 'C6x Internal Peripheral Register Values Register 0x0180 001C 0x0180 0018 0x0180 0014 Figure 4 DSP Memory Map Part Number 500-00191 13 14 Figure 5 DSP Memory Map for External-Memory Space CE1 2.2. Synchronous Burst SRAM 2.3. Synchronous DRAM 2.4. Processor Expansion Module 2.5. Host Port 2.6. Interrupt Lines 2.7. Processor Booting Part Number 500-00191 17 2.8. Serial Port Routing Figure 6 Serial Port Routing Node D Node C Node B 18 Table 7 VME and PMC Connections for Serial Port 1 3 Global Shared Bus via SCV64 3.1. Memory 3.2. Arbitration 3.2.1. Single Cycle Bus Access 3.2.2. Burst Cycle Bus Access 3.2.3. Locked Cycles Page 4 VME64 Bus Interface 4.1. VME Operation 4.2. SCV64 Primary Slave A32/A24 Interface 4.3. A24 Secondary Slave Interface VME64 Bus Interface all addresses mapped to 00 2008h all addresses mapped to 00 5008h all addresses mapped to 00 4008h all addresses mapped to 00 3008h Page 4.4. Master A32/A24/A16 SCV64 Interface Page 5 DSP~LINK3 Interface 5.1. DSP~LINK3 Data Transfer Operating Modes 5.2. Address Strobe Control Mode 5.3. Interface Signals 5.4. DSP~LINK3 Reset Page 6 PCI Interface 6.1. Hurricane Configuration PCI Interface 34 Table 11 Hurricane Register Set PCI Interface Part Number 500-00191 35 6.2. Hurricane Implementation 7 JTAG Debugging Page 8 Interrupt Handling 8.1. Overview Interrupt Handling 40 Figure 12 Interrupt Routing 8.2. DSP~LINK3 Interrupts to Node A 8.3. PEM Interrupts 8.4. PCI Bus Interrupts 8.5. Hurricane Interrupt 8.6. SCV64 Interrupt Page 8.7. Bus Error Interrupts 8.8. Inter-processor Interrupts 8.9. VME Host Interrupts To Any Node 9 Registers VPAGE Register VSTATUS Register Page VINTA Register VINTB Register VINTC Register VINTD Register KIPL Enable Register DSP~LINK3 Register ID Register VME A24 Status Register VME A24 Control Register Page 10 Specifications 10.1. Board Identification 10.2. General Specifications Part Number 500-00191 61 10.3. Performance and Data Throughput Page Part Number 500-00191 63 11 Connector Pinouts Node D Figure 13 Connector Layout Node C Node B 11.1. VME Connectors Part Number 500-00191 65 Table 17 VME P2 Connector Pinout (PMC to VME P2) 66 Table 18 VME P2 Connector (DSP~LINK3 to VME P2) Part Number 500-00191 67 11.2. PMC Connectors 68 Table 20 PMC Connector JN2 Part Number 500-00191 69 Table 21 PMC Connector JN4 70 Table 22 Non-standard PMC Connector JN5 Part Number 500-00191 71 11.3. PEM Connectors 72 Table 24 PEM 2 Connector Pinout Part Number 500-00191 73 11.4. JTAG Connectors Both JTAG connectors use 2 x 7, 0.1 x 0.1 bare pin headers. Table 25 JTAG IN Connector Pinout Table 26 JTAG OUT Connector Page SCV64 Register Values Part Number 500-00191 75 Appendix A: SCV64 Register Values SCV64 Register Values 76 Table 27 SCV64 Register Initialization Index A B C D E F G H I K L M P R T V