Kipl Enable Register, Kiplend, Kiplenc | Spectrum Brands C6x VME64

Spectrum Signal Processing	Monaco Technical Reference
	Registers

KIPL Enable Register

Address: 016D 8014h

D31..						..D8

		Reserved

D7..	..D4		D3	D2	D1	D0

Reserved			KIPL_END	KIPL_ENC	KIPL_ENB	KIPL_ENA

The KIPL Enable Register is used to enable interrupts generated from the SCV64 to be sent to a particular processor node. The /KIPL lines represent VME interrupts, location monitor interrupt, SCV64 DMA, and SCV64 timer interrupts. These enable bits do not affect the individual KBERR interrupt bits.

KIPL_END	When set to “1”, interrupts to node D that are generated from the SCV64
	/KIPL lines are enabled. Active high.

KIPL_ENC	When set to “1”, interrupts to node C that are generated from the SCV64
	/KIPL lines are enabled. Active high.

KIPL_ENB	When set to “1”, interrupts to node B that are generated from the SCV64
	/KIPL lines are enabled. Active high.

KIPL_ENA	When set to “1”, interrupts to node A that are generated from the SCV64
	/KIPL lines are enabled. Active high.

These bits are set to “0” upon reset.

Note: /KIPL interrupts must also be enabled by register writes to the SCV64.

Refer to the SCV64 data book for further information.

Part Number 500-00191	53
Revision 2.00

Image 65

Spectrum Brands C6x VME64 manual Kipl Enable Register, Kiplend, Kiplenc, Kiplenb, Kiplena

Contents

Monaco Revision Iii Preface History Document Rev Date ChangesChange Table of Contents Monaco Technical Reference Vii Viii List of Figures Table of Contents List of Tables Xii Product Operation Processors FeaturesIntroduction VME InterfacesPMC PEM Reference Documents General Bus Architecture On-Board Power Supply VME A24 Slave Interface Reset Reset ConditionsJtag Reset Sysreset Board Layout Board Layout OUT Jumper settingsJumper Settings Description Part Number Processor Nodes Processor Configurations Populated Processor Node Block Diagram External Memory Processor Memory ConfigurationInternal Memory 0x0180 DSP Memory Map Nodes B, C, and D Address Synchronous Dram Synchronous Burst SramProcessor Expansion Module Host Port Processor Boot Source Jumpers Node Processor Booting Serial Port Routing Serial Port Routing VME and PMC Connections for Serial Port PEM Connections for Serial Port 0 Global Shared Bus Global Shared Bus Access Source TargetMemory Arbitration Burst Cycle Bus Access Single Cycle Bus Access Locked Cycles Global Shared Bus SCV64 Primary Slave A32/A24 Interface VME64 Bus InterfaceVME Operation A24 Secondary Slave Interface Access A24 Secondary Interface Memory Map Hpia HPI Register Addresses VME address Master A32/A24/A16 SCV64 Interface VME64 Bus Interface DSP~LINK3 Data Transfer Operating Modes DSP~LINK3 Interface Astrben Address Strobe Control Mode DSP~LINK3 Reset Interface Signals DSP~LINK3 Interface PCI Offset Address Hurricane ConfigurationPCI Interface Value Initialize Hurricane Register Set BCC2A PCI Device Hurricane Implementation Jtag Chain Jtag Debugging Jtag Debugging Overview Interrupt Handling Interrupt Routing DSP~LINK3 Interrupts to Node a PCI Bus Interrupts PEM InterruptsHurricane Interrupt SCV64 Interrupt KIPL2 KIPL1 KIPL0 Kipl Status Bits and the Iack Cycle Bit Node Whose Access Caused the Bus Error Bus Error Interrupts VME Host Interrupts To Any Node Inter-processor Interrupts Registers Register Address Summary Access Privilege Bus KFC2..0 KSIZE1..0 KADDR1..0 Vpage Register Vstatus Register KIPL2..0 BuserraKavec Vinta Register Vintb Register Vintc Register Vintd Register Kiplend Kipl Enable RegisterKiplenc Kiplenb DSP~LINK3 Register DL3RESET ID Register Hinta VME A24 Status RegisterHintb Hintc VME A24 Control Register Registers Board Identification SpecificationsMonaco Monaco67 General Specifications Parameter Performance and Data Throughput Data Access/Transfer Performance Specifications Connector Layout Connector Pinouts VME P1 Connector Pinout VME Connectors VME P2 Connector Pinout PMC to VME P2 VME P2 Connector DSP~LINK3 to VME P2 PMC Connector JN1 Pinout PMC Connectors PMC Connector JN2 PMC Connector JN4 Non-standard PMC Connector JN5 PEM 1 Connector Pinout PEM Connectors PEM 2 Connector Pinout Jtag OUT Connector Jtag ConnectorsJtag in Connector Pinout Connector Pinouts SCV64 Register Initialization Appendix a SCV64 Register Values SCV64 Register Initialization VME Index Interrupts to node A, 40 register Reset Jtag Sysreset