DDR3DM0 | Xilinx ML605 specs

Chapter 1: ML605 Evaluation Board

Table 1-4:DDR3 SODIMM Connections (Cont’d)

U1 FPGA Pin	Schematic Net Name	J1 SODIMM
U1 FPGA Pin	Schematic Net Name
		Pin Number	Pin Name

E24	DDR3_D54	174	DQ54

G25	DDR3_D55	176	DQ55

F28	DDR3_D56	181	DQ56

B31	DDR3_D57	183	DQ57

H29	DDR3_D58	191	DQ58

H28	DDR3_D59	193	DQ59

B30	DDR3_D60	180	DQ60

A30	DDR3_D61	182	DQ61

E29	DDR3_D62	192	DQ62

F29	DDR3_D63	194	DQ63

E11	DDR3_DM0	11	DM0

B11	DDR3_DM1	28	DM1

E14	DDR3_DM2	46	DM2

D19	DDR3_DM3	63	DM3

B22	DDR3_DM4	136	DM4

A26	DDR3_DM5	153	DM5

A29	DDR3_DM6	170	DM6

A31	DDR3_DM7	187	DM7


E12	DDR3_DQS0_N	10	DQS0_N

D12	DDR3_DQS0_P	12	DQS0_P

J12	DDR3_DQS1_N	27	DQS1_N

H12	DDR3_DQS1_P	29	DQS1_P

A14	DDR3_DQS2_N	45	DQS2_N

A13	DDR3_DQS2_P	47	DQS2_P

H20	DDR3_DQS3_N	62	DQS3_N

H19	DDR3_DQS3_P	64	DQS3_P

C23	DDR3_DQS4_N	135	DQS4_N

B23	DDR3_DQS4_P	137	DQS4_P

A25	DDR3_DQS5_N	152	DQS5_N

B25	DDR3_DQS5_P	154	DQS5_P

G28	DDR3_DQS6_N	169	DQS6_N

H27	DDR3_DQS6_P	171	DQS6_P

D30	DDR3_DQS7_N	186	DQS7_N

18	www.xilinx.com	ML605 Hardware User Guide
		UG534 (v1.2.1) January 21, 2010

Image 18

Xilinx ML605 manual DDR3DM0

Contents

ML605 Hardware User Guide UG534 v1.2.1 January 21, 2010 optional Revision History Date Version Revision Table of Contents ML605 Hardware User Guide About This Guide Additional Support Resources Preface About This Guide ML605 Evaluation Board Additional Information SMA FeaturesML605 Evaluation Board IIC Eeprom 1 KB Overview Fpga Init Fpga Done Block Diagram 1ML605 High-Level Block Diagram Detailed Description ML605 FeaturesFeature DDR3 Sodimm ML605 Evaluation Board ML605 Features Cont’d SgmiiWDW6TP Configuration Virtex-6 XC6VLX240T-1FFG1156 Fpga Cclk Direction 2Virtex-6 Fpga Configuration Modes M20Voltage Rails 3Voltage Rails U1 Fpga Bank VCC1V5FPGA MB DDR3 Memory SodimmDetailed Description 3Voltage Rails Cont’d U1 Fpga Bank 4DDR3 Sodimm Connections ML605 Evaluation Board 4DDR3 Sodimm Connections Cont’d DDR3A9 DDR3D30 DQ30 DDR3DM0 See the Micron Technology, Inc. for more information Ref Mb Platform Flash XL MB Linear BPI Flash ML605 Flash Boot Options FLASHD2 DQ2 FLASHD0 DQ0FLASHD1 DQ1 FLASHD3 DQ3 Fpga Design Considerations for the Configuration Flash System ACE CF and CompactFlash Connector 6System ACE CF Connections U1 Fpga Pin Schematic Net Name USB Jtag Clock Generation Oscillator DifferentialOscillator Socket Single-Ended 7ML605 Oscillator Socket Pin 1 Location Identifiers SMA Connectors Differential 8ML605 Oscillator Pin 1 Location Identifiers SMA Pin SmarefclknSmarefclkp Multi-Gigabit Transceivers GTX MGTs ICS PCI Express Endpoint Connectivity 12PCIe Lane Size Select Jumper J42 8PCIe Edge Connector Connections PCIE100MMGT0P AA3 PCIERX7PAA4 PCIERX7N GTXE1X0Y6 SFP Module Connector 11 /100/1000 Tri-Speed Ethernet PHY 11PHY Default Interface Mode Jumper Settings J66 J67 J6812Board Connections for PHY Configuration Pins Bit2 Bit1 Bit0 13Ethernet PHYConnections U1 Fpga Pin 12Board Connections for PHY Configuration Pins Cont’dSgmii GTX Transceiver Clock Generation U80 M88E1111 PHYRXD5 PHYRXD4RXD4 RXD5 USB-to-UART Bridge VbusGround USB Controller 16USB Controller ConnectionsU81 USB Controller DVI Codec 17DVI Controller ConnectionsU38 Chrontel CH7301C IIC Bus 14IIC Bus Topology Kb NV Memory Iicsdamain SDAIicsclmain SCL Designator Signal Name Color Label Description Status LEDs Ethernet PHY Status LEDs 16Ethernet PHY Status LEDs Controlled LED User I/OFpga Init and Done LEDs Fpgainitb 18User LEDs and Gpio Connector, Directional LEDs User LEDs User Pushbutton Switches Detailed Description 21User LED Connections Fpga U1 PinGpio J62 Pin Controlled LED User DIP Switch Switch Pin User SMA Gpio UsersmagpionUsersmagpiop LCD Display 16 Character x 2 Lines J41 Pin Switches Power On/Off Slide Switch SW2 Sysaceresetb Pushbutton SW3 Active-Low Fpgaprogb Pushbutton SW4 Active-Low System ACE CF CompactFlash Image Select DIP Switch S1 26System ACE CF CompactFlash Image Select DIP Switch S1 26ML605 Configuration Modes M20 Bus Width Vita 57.1 FMC HPC Connector Master BPI 28VITA 57.1 FMC HPC Connections HPC Pin 28VITA 57.1 FMC HPC Connections Cont’d FMCHPCHB13P FMCHPCHB09NFMCHPCHB08P FMCHPCHB08N Detailed Description 28VITA 57.1 FMC HPC Connections Cont’d VREFAM2C Vadj VadjVIOBM2C Vadj VREFBM2C Vita 57.1 FMC LPC Connector 30VITA 57.1 FMC LPC Connections LPC Pin Power Management AC Adapter and Input Power Jack/SwitchDetailed Description 30VITA 57.1 FMC LPC Connections Cont’d Onboard Power Regulation 28ML605 Onboard Power Regulators Vccaux UCD9240PFCVccintfpga UCD7230RGWR System Monitor 29System Monitor External Reference System Monitor Header J35 12V Supply Monitor Fan Controller Bank Configuration Options Configuration Options ML605 Evaluation Board Table A-1Default Switch Settings Function/Type Default Gmii Vita 57.1 FMC LPC J63 and HPC J64 Connector Pinout Figure B-2FMC HPC Connector Pinout ML605 Master UCF Appendix C ML605 Master UCF NET DDR3D9 NET DDR3DQS0P NET FLASHA21 ML605 Hardware User Guide UG534 v1.2.1 January 21 NET FMCHPCHB03P NET FMCHPCLA16N NET FMCLPCPRSNTM2CL NET Iicsdadvi NET PCIERX2N NET Pmbusdatals NET Sfplos NET Sfprxn NET Sfprxp NET USBD6LS References Appendix D References