PHYRXD4, PHYRXD5, PHYRXD6, PHYRXD7, Phytxclk Txclk | Xilinx ML605

Chapter 1: ML605 Evaluation Board

Table 1-13:Ethernet PHYConnections (Cont’d)

	U1 FPGA Pin	Schematic Net Name	U80 M88E1111

			Pin Number	Pin Name
			Pin Number	Pin Name

	AM12	PHY_RXD4	124	RXD4

	AD11	PHY_RXD5	123	RXD5

	AC12	PHY_RXD6	121	RXD6

	AC13	PHY_RXD7	120	RXD7

	AH12	PHY_TXC_GTXCLK	14	GTXCLK

	AD12	PHY_TXCLK	10	TXCLK

	AH10	PHY_TXER	13	TXER

	AJ10	PHY_TXCTL_TXEN	16	TXEN

	AM11	PHY_TXD0	18	TXD0

	AL11	PHY_TXD1	19	TXD1

	AG10	PHY_TXD2	20	TXD2

	AG11	PHY_TXD3	24	TXD3

	AL10	PHY_TXD4	25	TXD4

	AM10	PHY_TXD5	26	TXD5

	AE11	PHY_TXD6	28	TXD6

	AF11	PHY_TXD7	29	TXD7

	A3	SGMII_TX_P	113	SIN_P

	A4	SGMII_TX_N	112	SIN_N

	B5	SGMII_RX_P	107	SOUT_P

	B6	SGMII_RX_N	105	SOUT_N

References

See the Marvell Alaska Gigabit Ethernet Transceivers product page for more information. [Ref 28]

Also, see the LogiCORE™ IP Tri-Mode Ethernet MAC User Guide. [Ref 19]

38	www.xilinx.com	ML605 Hardware User Guide
		UG534 (v1.2.1) January 21, 2010

Image 38

Xilinx ML605 PHYRXD4, PHYRXD5, PHYRXD6, PHYRXD7, Phytxcgtxclk Gtxclk, Phytxclk Txclk, Phytxer Txer, Phytxctltxen Txen

Contents

ML605 Hardware User Guide UG534 v1.2.1 January 21, 2010 optional Revision History Date Version Revision Table of Contents ML605 Hardware User Guide About This Guide Additional Support Resources Preface About This Guide ML605 Evaluation Board Additional Information SMA FeaturesML605 Evaluation Board IIC Eeprom 1 KB Overview Fpga Init Fpga Done Block Diagram 1ML605 High-Level Block Diagram Detailed Description ML605 FeaturesFeature DDR3 Sodimm WDW6TP ML605 Evaluation Board ML605 Features Cont’dSgmii Configuration Virtex-6 XC6VLX240T-1FFG1156 Fpga Cclk Direction 2Virtex-6 Fpga Configuration Modes M20Voltage Rails 3Voltage Rails U1 Fpga Bank VCC1V5FPGA MB DDR3 Memory SodimmDetailed Description 3Voltage Rails Cont’d U1 Fpga Bank 4DDR3 Sodimm Connections ML605 Evaluation Board 4DDR3 Sodimm Connections Cont’d DDR3A9 DDR3D30 DQ30 DDR3DM0 See the Micron Technology, Inc. for more information Ref Mb Platform Flash XL MB Linear BPI Flash ML605 Flash Boot Options FLASHD2 DQ2 FLASHD0 DQ0FLASHD1 DQ1 FLASHD3 DQ3 Fpga Design Considerations for the Configuration Flash System ACE CF and CompactFlash Connector 6System ACE CF Connections U1 Fpga Pin Schematic Net Name USB Jtag Oscillator Socket Single-Ended Clock GenerationOscillator Differential 7ML605 Oscillator Socket Pin 1 Location Identifiers SMA Connectors Differential 8ML605 Oscillator Pin 1 Location Identifiers Smarefclkp SMA PinSmarefclkn Multi-Gigabit Transceivers GTX MGTs ICS PCI Express Endpoint Connectivity 12PCIe Lane Size Select Jumper J42 8PCIe Edge Connector Connections PCIE100MMGT0P AA3 PCIERX7PAA4 PCIERX7N GTXE1X0Y6 SFP Module Connector 11 /100/1000 Tri-Speed Ethernet PHY 11PHY Default Interface Mode Jumper Settings J66 J67 J6812Board Connections for PHY Configuration Pins Bit2 Bit1 Bit0 13Ethernet PHYConnections U1 Fpga Pin 12Board Connections for PHY Configuration Pins Cont’dSgmii GTX Transceiver Clock Generation U80 M88E1111 PHYRXD5 PHYRXD4RXD4 RXD5 Ground USB-to-UART BridgeVbus U81 USB Controller USB Controller16USB Controller Connections U38 Chrontel CH7301C DVI Codec17DVI Controller Connections IIC Bus 14IIC Bus Topology Iicsclmain SCL Kb NV MemoryIicsdamain SDA Designator Signal Name Color Label Description Status LEDs Ethernet PHY Status LEDs 16Ethernet PHY Status LEDs Controlled LED User I/OFpga Init and Done LEDs Fpgainitb 18User LEDs and Gpio Connector, Directional LEDs User LEDs Gpio J62 Pin Controlled LED User Pushbutton SwitchesDetailed Description 21User LED Connections Fpga U1 Pin User DIP Switch Switch Pin Usersmagpiop User SMA GpioUsersmagpion LCD Display 16 Character x 2 Lines J41 Pin Switches Power On/Off Slide Switch SW2 Sysaceresetb Pushbutton SW3 Active-Low Fpgaprogb Pushbutton SW4 Active-Low System ACE CF CompactFlash Image Select DIP Switch S1 26System ACE CF CompactFlash Image Select DIP Switch S1 26ML605 Configuration Modes M20 Bus Width Vita 57.1 FMC HPC Connector Master BPI 28VITA 57.1 FMC HPC Connections HPC Pin 28VITA 57.1 FMC HPC Connections Cont’d FMCHPCHB13P FMCHPCHB09NFMCHPCHB08P FMCHPCHB08N Detailed Description 28VITA 57.1 FMC HPC Connections Cont’d VREFAM2C Vadj VadjVIOBM2C Vadj VREFBM2C Vita 57.1 FMC LPC Connector 30VITA 57.1 FMC LPC Connections LPC Pin Detailed Description 30VITA 57.1 FMC LPC Connections Cont’d Power ManagementAC Adapter and Input Power Jack/Switch Onboard Power Regulation 28ML605 Onboard Power Regulators Vccaux UCD9240PFCVccintfpga UCD7230RGWR System Monitor 29System Monitor External Reference System Monitor Header J35 12V Supply Monitor Fan Controller Bank Configuration Options Configuration Options ML605 Evaluation Board Table A-1Default Switch Settings Function/Type Default Gmii Vita 57.1 FMC LPC J63 and HPC J64 Connector Pinout Figure B-2FMC HPC Connector Pinout ML605 Master UCF Appendix C ML605 Master UCF NET DDR3D9 NET DDR3DQS0P NET FLASHA21 ML605 Hardware User Guide UG534 v1.2.1 January 21 NET FMCHPCHB03P NET FMCHPCLA16N NET FMCLPCPRSNTM2CL NET Iicsdadvi NET PCIERX2N NET Pmbusdatals NET Sfplos NET Sfprxn NET Sfprxp NET USBD6LS References Appendix D References